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Macros</h2></td></tr>
<tr class="memitem:gac9f8c8a63f0b462fe9d58b097ce69e8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac9f8c8a63f0b462fe9d58b097ce69e8a">XRFdc_ReadReg64</a>(InstancePtr, BaseAddress, RegOffset)&#160;&#160;&#160;XRFdc_In64(InstancePtr-&gt;io, ((u32)RegOffset + (u32)BaseAddress))</td></tr>
<tr class="memdesc:gac9f8c8a63f0b462fe9d58b097ce69e8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group___overview.html#gac9f8c8a63f0b462fe9d58b097ce69e8a">More...</a><br/></td></tr>
<tr class="separator:gac9f8c8a63f0b462fe9d58b097ce69e8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48b65f7c1f2e3b221e27261a1d2c4ec3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga48b65f7c1f2e3b221e27261a1d2c4ec3">XRFdc_WriteReg64</a>(InstancePtr, BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XRFdc_Out64((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:ga48b65f7c1f2e3b221e27261a1d2c4ec3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group___overview.html#ga48b65f7c1f2e3b221e27261a1d2c4ec3">More...</a><br/></td></tr>
<tr class="separator:ga48b65f7c1f2e3b221e27261a1d2c4ec3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a731c664a38baba8f030dfa31da4cb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a731c664a38baba8f030dfa31da4cb3">XRFdc_ReadReg</a>(InstancePtr, BaseAddress, RegOffset)&#160;&#160;&#160;XRFdc_In32((InstancePtr-&gt;io), ((u32)BaseAddress + (u32)RegOffset))</td></tr>
<tr class="memdesc:ga9a731c664a38baba8f030dfa31da4cb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group___overview.html#ga9a731c664a38baba8f030dfa31da4cb3">More...</a><br/></td></tr>
<tr class="separator:ga9a731c664a38baba8f030dfa31da4cb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga325feda106c46bd899aa82ebc351c72d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga325feda106c46bd899aa82ebc351c72d">XRFdc_WriteReg</a>(InstancePtr, BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XRFdc_Out32((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:ga325feda106c46bd899aa82ebc351c72d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group___overview.html#ga325feda106c46bd899aa82ebc351c72d">More...</a><br/></td></tr>
<tr class="separator:ga325feda106c46bd899aa82ebc351c72d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0617225f23684b78001b141ad96d5ee5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0617225f23684b78001b141ad96d5ee5">XRFdc_ReadReg16</a>(InstancePtr, BaseAddress, RegOffset)&#160;&#160;&#160;XRFdc_In16((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress))</td></tr>
<tr class="memdesc:ga0617225f23684b78001b141ad96d5ee5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group___overview.html#ga0617225f23684b78001b141ad96d5ee5">More...</a><br/></td></tr>
<tr class="separator:ga0617225f23684b78001b141ad96d5ee5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad87e168d6ea69d69382b9212aa1267ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad87e168d6ea69d69382b9212aa1267ba">XRFdc_WriteReg16</a>(InstancePtr, BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XRFdc_Out16((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:gad87e168d6ea69d69382b9212aa1267ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group___overview.html#gad87e168d6ea69d69382b9212aa1267ba">More...</a><br/></td></tr>
<tr class="separator:gad87e168d6ea69d69382b9212aa1267ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c1ddd61213bde8ea4d392532e8d0dbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8c1ddd61213bde8ea4d392532e8d0dbb">XRFdc_ReadReg8</a>(InstancePtr, BaseAddress, RegOffset)&#160;&#160;&#160;XRFdc_In8((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress))</td></tr>
<tr class="memdesc:ga8c1ddd61213bde8ea4d392532e8d0dbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group___overview.html#ga8c1ddd61213bde8ea4d392532e8d0dbb">More...</a><br/></td></tr>
<tr class="separator:ga8c1ddd61213bde8ea4d392532e8d0dbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa10f5b7c24b2d9c3faa14a8cab8ae1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa10f5b7c24b2d9c3faa14a8cab8ae1db">XRFdc_WriteReg8</a>(InstancePtr, BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XRFdc_Out8((InstancePtr-&gt;io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:gaa10f5b7c24b2d9c3faa14a8cab8ae1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group___overview.html#gaa10f5b7c24b2d9c3faa14a8cab8ae1db">More...</a><br/></td></tr>
<tr class="separator:gaa10f5b7c24b2d9c3faa14a8cab8ae1db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets from the base address of an RFDC ADC and DAC device. </p>
</div></td></tr>
<tr class="memitem:gad414fcd2907e700f3fb0c67b0ec982f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad414fcd2907e700f3fb0c67b0ec982f8">XRFDC_CLK_EN_OFFSET</a>&#160;&#160;&#160;0x000U</td></tr>
<tr class="memdesc:gad414fcd2907e700f3fb0c67b0ec982f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Clock Enable Register.  <a href="group___overview.html#gad414fcd2907e700f3fb0c67b0ec982f8">More...</a><br/></td></tr>
<tr class="separator:gad414fcd2907e700f3fb0c67b0ec982f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc8b1508d65831d7ecfc17ada17d8e21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadc8b1508d65831d7ecfc17ada17d8e21">XRFDC_ADC_DEBUG_RST_OFFSET</a>&#160;&#160;&#160;0x004U</td></tr>
<tr class="memdesc:gadc8b1508d65831d7ecfc17ada17d8e21"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Debug Reset Register.  <a href="group___overview.html#gadc8b1508d65831d7ecfc17ada17d8e21">More...</a><br/></td></tr>
<tr class="separator:gadc8b1508d65831d7ecfc17ada17d8e21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22d11bb8767ab5d566fbd01f8e4e0f96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga22d11bb8767ab5d566fbd01f8e4e0f96">XRFDC_ADC_FABRIC_RATE_OFFSET</a>&#160;&#160;&#160;0x008U</td></tr>
<tr class="memdesc:ga22d11bb8767ab5d566fbd01f8e4e0f96"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Rate Register.  <a href="group___overview.html#ga22d11bb8767ab5d566fbd01f8e4e0f96">More...</a><br/></td></tr>
<tr class="separator:ga22d11bb8767ab5d566fbd01f8e4e0f96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga680d43872c8864772f1333ed2ff55bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga680d43872c8864772f1333ed2ff55bf6">XRFDC_ADC_FABRIC_RATE_OBS_OFFSET</a>&#160;&#160;&#160;0x050U</td></tr>
<tr class="memdesc:ga680d43872c8864772f1333ed2ff55bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Obs Fabric Rate Register.  <a href="group___overview.html#ga680d43872c8864772f1333ed2ff55bf6">More...</a><br/></td></tr>
<tr class="separator:ga680d43872c8864772f1333ed2ff55bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaca84481089d75d4874910b669cc0869"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaaca84481089d75d4874910b669cc0869">XRFDC_ADC_FABRIC_RATE_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:gaaca84481089d75d4874910b669cc0869"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Rate (or OBS) Register TDD Selected.  <a href="group___overview.html#gaaca84481089d75d4874910b669cc0869">More...</a><br/></td></tr>
<tr class="separator:gaaca84481089d75d4874910b669cc0869"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e0ee1cc083a1840bb17eec5f3f53c21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4e0ee1cc083a1840bb17eec5f3f53c21">XRFDC_DAC_FABRIC_RATE_OFFSET</a>&#160;&#160;&#160;0x008U</td></tr>
<tr class="memdesc:ga4e0ee1cc083a1840bb17eec5f3f53c21"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Fabric Rate Register.  <a href="group___overview.html#ga4e0ee1cc083a1840bb17eec5f3f53c21">More...</a><br/></td></tr>
<tr class="separator:ga4e0ee1cc083a1840bb17eec5f3f53c21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc7664790ca254ad00577f7a968e2280"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacc7664790ca254ad00577f7a968e2280">XRFDC_ADC_FABRIC_OFFSET</a>&#160;&#160;&#160;0x00CU</td></tr>
<tr class="memdesc:gacc7664790ca254ad00577f7a968e2280"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Register.  <a href="group___overview.html#gacc7664790ca254ad00577f7a968e2280">More...</a><br/></td></tr>
<tr class="separator:gacc7664790ca254ad00577f7a968e2280"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96e6c66fb3e3c2b941e217713a73131c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga96e6c66fb3e3c2b941e217713a73131c">XRFDC_ADC_FABRIC_OBS_OFFSET</a>&#160;&#160;&#160;0x054U</td></tr>
<tr class="memdesc:ga96e6c66fb3e3c2b941e217713a73131c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Obs Fabric Register.  <a href="group___overview.html#ga96e6c66fb3e3c2b941e217713a73131c">More...</a><br/></td></tr>
<tr class="separator:ga96e6c66fb3e3c2b941e217713a73131c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5219074f9fb39992d524f9a57cc4a7aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5219074f9fb39992d524f9a57cc4a7aa">XRFDC_ADC_FABRIC_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:ga5219074f9fb39992d524f9a57cc4a7aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Register (or OBS) TDD Selected.  <a href="group___overview.html#ga5219074f9fb39992d524f9a57cc4a7aa">More...</a><br/></td></tr>
<tr class="separator:ga5219074f9fb39992d524f9a57cc4a7aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga812676621b88662c3fa99a69131d8bf7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga812676621b88662c3fa99a69131d8bf7">XRFDC_ADC_FABRIC_ISR_OFFSET</a>&#160;&#160;&#160;0x010U</td></tr>
<tr class="memdesc:ga812676621b88662c3fa99a69131d8bf7"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric ISR Register.  <a href="group___overview.html#ga812676621b88662c3fa99a69131d8bf7">More...</a><br/></td></tr>
<tr class="separator:ga812676621b88662c3fa99a69131d8bf7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8981438e66b6c0be55e70dea7cacb58d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8981438e66b6c0be55e70dea7cacb58d">XRFDC_DAC_FIFO_START_OFFSET</a>&#160;&#160;&#160;0x010U</td></tr>
<tr class="memdesc:ga8981438e66b6c0be55e70dea7cacb58d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO Start Register.  <a href="group___overview.html#ga8981438e66b6c0be55e70dea7cacb58d">More...</a><br/></td></tr>
<tr class="separator:ga8981438e66b6c0be55e70dea7cacb58d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga710b4810bc6d4f845a743d52d337b824"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga710b4810bc6d4f845a743d52d337b824">XRFDC_DAC_FABRIC_ISR_OFFSET</a>&#160;&#160;&#160;0x014U</td></tr>
<tr class="memdesc:ga710b4810bc6d4f845a743d52d337b824"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Fabric ISR Register.  <a href="group___overview.html#ga710b4810bc6d4f845a743d52d337b824">More...</a><br/></td></tr>
<tr class="separator:ga710b4810bc6d4f845a743d52d337b824"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae8d0fd30082364e9c6e1492d9861356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaae8d0fd30082364e9c6e1492d9861356">XRFDC_ADC_FABRIC_IMR_OFFSET</a>&#160;&#160;&#160;0x014U</td></tr>
<tr class="memdesc:gaae8d0fd30082364e9c6e1492d9861356"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric IMR Register.  <a href="group___overview.html#gaae8d0fd30082364e9c6e1492d9861356">More...</a><br/></td></tr>
<tr class="separator:gaae8d0fd30082364e9c6e1492d9861356"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadec02b825d78a1a837c763b963784f4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadec02b825d78a1a837c763b963784f4d">XRFDC_DAC_FABRIC_IMR_OFFSET</a>&#160;&#160;&#160;0x018U</td></tr>
<tr class="memdesc:gadec02b825d78a1a837c763b963784f4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Fabric IMR Register.  <a href="group___overview.html#gadec02b825d78a1a837c763b963784f4d">More...</a><br/></td></tr>
<tr class="separator:gadec02b825d78a1a837c763b963784f4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga49a9f3a64f3fa49b9b88b6ef4e87def1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga49a9f3a64f3fa49b9b88b6ef4e87def1">XRFDC_ADC_FABRIC_DBG_OFFSET</a>&#160;&#160;&#160;0x018U</td></tr>
<tr class="memdesc:ga49a9f3a64f3fa49b9b88b6ef4e87def1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Debug Register.  <a href="group___overview.html#ga49a9f3a64f3fa49b9b88b6ef4e87def1">More...</a><br/></td></tr>
<tr class="separator:ga49a9f3a64f3fa49b9b88b6ef4e87def1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9df7a4f2bdb3775ecaaf21d4abe21888"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9df7a4f2bdb3775ecaaf21d4abe21888">XRFDC_ADC_FABRIC_DBG_OBS_OFFSET</a>&#160;&#160;&#160;0x058U</td></tr>
<tr class="memdesc:ga9df7a4f2bdb3775ecaaf21d4abe21888"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Obs Fabric Debug Register.  <a href="group___overview.html#ga9df7a4f2bdb3775ecaaf21d4abe21888">More...</a><br/></td></tr>
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<tr class="memitem:ga2a2a2d0c2b8e53847196c67bdd992c99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2a2a2d0c2b8e53847196c67bdd992c99">XRFDC_ADC_FABRIC_DBG_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:ga2a2a2d0c2b8e53847196c67bdd992c99"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric Debug (or OBS) Register TDD Selected.  <a href="group___overview.html#ga2a2a2d0c2b8e53847196c67bdd992c99">More...</a><br/></td></tr>
<tr class="separator:ga2a2a2d0c2b8e53847196c67bdd992c99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga122ceb1d0f0a5759d11e1c3b092b1de4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga122ceb1d0f0a5759d11e1c3b092b1de4">XRFDC_ADC_UPDATE_DYN_OFFSET</a>&#160;&#160;&#160;0x01CU</td></tr>
<tr class="memdesc:ga122ceb1d0f0a5759d11e1c3b092b1de4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Update Dynamic Register.  <a href="group___overview.html#ga122ceb1d0f0a5759d11e1c3b092b1de4">More...</a><br/></td></tr>
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<tr class="memitem:gabbf203eff6b1c80ae2eab5524e736622"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabbf203eff6b1c80ae2eab5524e736622">XRFDC_DAC_UPDATE_DYN_OFFSET</a>&#160;&#160;&#160;0x020U</td></tr>
<tr class="memdesc:gabbf203eff6b1c80ae2eab5524e736622"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Update Dynamic Register.  <a href="group___overview.html#gabbf203eff6b1c80ae2eab5524e736622">More...</a><br/></td></tr>
<tr class="separator:gabbf203eff6b1c80ae2eab5524e736622"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1007bbbd1a42619b1e77246d6ee5e524"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1007bbbd1a42619b1e77246d6ee5e524">XRFDC_ADC_FIFO_LTNC_CRL_OFFSET</a>&#160;&#160;&#160;0x020U</td></tr>
<tr class="memdesc:ga1007bbbd1a42619b1e77246d6ee5e524"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Latency Control Register.  <a href="group___overview.html#ga1007bbbd1a42619b1e77246d6ee5e524">More...</a><br/></td></tr>
<tr class="separator:ga1007bbbd1a42619b1e77246d6ee5e524"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5608b2e4e1b439bde04ac8b61bafd544"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5608b2e4e1b439bde04ac8b61bafd544">XRFDC_ADC_FIFO_LTNC_CRL_OBS_OFFSET</a>&#160;&#160;&#160;0x064U</td></tr>
<tr class="memdesc:ga5608b2e4e1b439bde04ac8b61bafd544"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Obs FIFO Latency Control Register.  <a href="group___overview.html#ga5608b2e4e1b439bde04ac8b61bafd544">More...</a><br/></td></tr>
<tr class="separator:ga5608b2e4e1b439bde04ac8b61bafd544"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1b589ddc5fe21074d2995abada16cc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa1b589ddc5fe21074d2995abada16cc5">XRFDC_ADC_FIFO_LTNC_CRL_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:gaa1b589ddc5fe21074d2995abada16cc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Latency Control (or OBS) Register TDD Selected.  <a href="group___overview.html#gaa1b589ddc5fe21074d2995abada16cc5">More...</a><br/></td></tr>
<tr class="separator:gaa1b589ddc5fe21074d2995abada16cc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dca150079590927aacc387663dfc9c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5dca150079590927aacc387663dfc9c5">XRFDC_ADC_DEC_ISR_OFFSET</a>&#160;&#160;&#160;0x030U</td></tr>
<tr class="memdesc:ga5dca150079590927aacc387663dfc9c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decoder interface ISR Register.  <a href="group___overview.html#ga5dca150079590927aacc387663dfc9c5">More...</a><br/></td></tr>
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<tr class="memitem:ga4cf5ab6c54a67d3797ca786b4c14be22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4cf5ab6c54a67d3797ca786b4c14be22">XRFDC_DAC_DATAPATH_OFFSET</a>&#160;&#160;&#160;0x034U</td></tr>
<tr class="memdesc:ga4cf5ab6c54a67d3797ca786b4c14be22"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decoder interface IMR Register.  <a href="group___overview.html#ga4cf5ab6c54a67d3797ca786b4c14be22">More...</a><br/></td></tr>
<tr class="separator:ga4cf5ab6c54a67d3797ca786b4c14be22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab9e237efa681e56c07512e2abf42e49b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab9e237efa681e56c07512e2abf42e49b">XRFDC_ADC_DEC_IMR_OFFSET</a>&#160;&#160;&#160;0x034U</td></tr>
<tr class="memdesc:gab9e237efa681e56c07512e2abf42e49b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decoder interface IMR Register.  <a href="group___overview.html#gab9e237efa681e56c07512e2abf42e49b">More...</a><br/></td></tr>
<tr class="separator:gab9e237efa681e56c07512e2abf42e49b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga177754ef4dacef7d7b62b82b7067093f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga177754ef4dacef7d7b62b82b7067093f">XRFDC_DATPATH_ISR_OFFSET</a>&#160;&#160;&#160;0x038U</td></tr>
<tr class="memdesc:ga177754ef4dacef7d7b62b82b7067093f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Data Path ISR Register.  <a href="group___overview.html#ga177754ef4dacef7d7b62b82b7067093f">More...</a><br/></td></tr>
<tr class="separator:ga177754ef4dacef7d7b62b82b7067093f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf44fa273f4e1ae98251eb2c788ecb82b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf44fa273f4e1ae98251eb2c788ecb82b">XRFDC_DATPATH_IMR_OFFSET</a>&#160;&#160;&#160;0x03CU</td></tr>
<tr class="memdesc:gaf44fa273f4e1ae98251eb2c788ecb82b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Data Path IMR Register.  <a href="group___overview.html#gaf44fa273f4e1ae98251eb2c788ecb82b">More...</a><br/></td></tr>
<tr class="separator:gaf44fa273f4e1ae98251eb2c788ecb82b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga99982520ba7d95d1a934a07fc07b3943"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga99982520ba7d95d1a934a07fc07b3943">XRFDC_ADC_DECI_CONFIG_OFFSET</a>&#160;&#160;&#160;0x040U</td></tr>
<tr class="memdesc:ga99982520ba7d95d1a934a07fc07b3943"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decimation Config Register.  <a href="group___overview.html#ga99982520ba7d95d1a934a07fc07b3943">More...</a><br/></td></tr>
<tr class="separator:ga99982520ba7d95d1a934a07fc07b3943"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d0081917c634d23aa69d9ac133448f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3d0081917c634d23aa69d9ac133448f1">XRFDC_ADC_DECI_CONFIG_OBS_OFFSET</a>&#160;&#160;&#160;0x048U</td></tr>
<tr class="memdesc:ga3d0081917c634d23aa69d9ac133448f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decimation Config Register.  <a href="group___overview.html#ga3d0081917c634d23aa69d9ac133448f1">More...</a><br/></td></tr>
<tr class="separator:ga3d0081917c634d23aa69d9ac133448f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50a2b319cf14929dd3638dded19c34ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga50a2b319cf14929dd3638dded19c34ae">XRFDC_ADC_DECI_CONFIG_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:ga50a2b319cf14929dd3638dded19c34ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decimation Config (or OBS) Register TDD Selected.  <a href="group___overview.html#ga50a2b319cf14929dd3638dded19c34ae">More...</a><br/></td></tr>
<tr class="separator:ga50a2b319cf14929dd3638dded19c34ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga500c30f98d7b3b461ea75a0d03a17e55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga500c30f98d7b3b461ea75a0d03a17e55">XRFDC_DAC_INTERP_CTRL_OFFSET</a>&#160;&#160;&#160;0x040U</td></tr>
<tr class="memdesc:ga500c30f98d7b3b461ea75a0d03a17e55"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Interpolation Control Register.  <a href="group___overview.html#ga500c30f98d7b3b461ea75a0d03a17e55">More...</a><br/></td></tr>
<tr class="separator:ga500c30f98d7b3b461ea75a0d03a17e55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a862371dfeb8508daf6da3338becbdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4a862371dfeb8508daf6da3338becbdb">XRFDC_ADC_DECI_MODE_OFFSET</a>&#160;&#160;&#160;0x044U</td></tr>
<tr class="memdesc:ga4a862371dfeb8508daf6da3338becbdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decimation mode Register.  <a href="group___overview.html#ga4a862371dfeb8508daf6da3338becbdb">More...</a><br/></td></tr>
<tr class="separator:ga4a862371dfeb8508daf6da3338becbdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fcb7530c54f07898c73e4a79d556dc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6fcb7530c54f07898c73e4a79d556dc8">XRFDC_ADC_DECI_MODE_OBS_OFFSET</a>&#160;&#160;&#160;0x04CU</td></tr>
<tr class="memdesc:ga6fcb7530c54f07898c73e4a79d556dc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Obs Decimation mode Register.  <a href="group___overview.html#ga6fcb7530c54f07898c73e4a79d556dc8">More...</a><br/></td></tr>
<tr class="separator:ga6fcb7530c54f07898c73e4a79d556dc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab432bb14feab21df380f1d76ed740eb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab432bb14feab21df380f1d76ed740eb4">XRFDC_ADC_DECI_MODE_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:gab432bb14feab21df380f1d76ed740eb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Decimation mode (or OBS) Register TDD Selected.  <a href="group___overview.html#gab432bb14feab21df380f1d76ed740eb4">More...</a><br/></td></tr>
<tr class="separator:gab432bb14feab21df380f1d76ed740eb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9291cdab5a8ff89253c5e4dbbd5771db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9291cdab5a8ff89253c5e4dbbd5771db">XRFDC_DAC_ITERP_DATA_OFFSET</a>&#160;&#160;&#160;0x044U</td></tr>
<tr class="memdesc:ga9291cdab5a8ff89253c5e4dbbd5771db"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC interpolation data.  <a href="group___overview.html#ga9291cdab5a8ff89253c5e4dbbd5771db">More...</a><br/></td></tr>
<tr class="separator:ga9291cdab5a8ff89253c5e4dbbd5771db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33c634e2c043b8256da76e247480bdf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga33c634e2c043b8256da76e247480bdf0">XRFDC_ADC_FABRIC_ISR_OBS_OFFSET</a>&#160;&#160;&#160;0x05CU</td></tr>
<tr class="memdesc:ga33c634e2c043b8256da76e247480bdf0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric ISR Observation Register.  <a href="group___overview.html#ga33c634e2c043b8256da76e247480bdf0">More...</a><br/></td></tr>
<tr class="separator:ga33c634e2c043b8256da76e247480bdf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb12af2443c1fc0e7f65f2650e9f951b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacb12af2443c1fc0e7f65f2650e9f951b">XRFDC_ADC_FABRIC_IMR_OBS_OFFSET</a>&#160;&#160;&#160;0x060U</td></tr>
<tr class="memdesc:gacb12af2443c1fc0e7f65f2650e9f951b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Fabric ISR Observation Register.  <a href="group___overview.html#gacb12af2443c1fc0e7f65f2650e9f951b">More...</a><br/></td></tr>
<tr class="separator:gacb12af2443c1fc0e7f65f2650e9f951b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f14ef7a113ef517ec2bff179ecfd837"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2f14ef7a113ef517ec2bff179ecfd837">XRFDC_DAC_TDD_MODE0_OFFSET</a>&#160;&#160;&#160;0x060U</td></tr>
<tr class="memdesc:ga2f14ef7a113ef517ec2bff179ecfd837"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC TDD Mode 0 Configuration.  <a href="group___overview.html#ga2f14ef7a113ef517ec2bff179ecfd837">More...</a><br/></td></tr>
<tr class="separator:ga2f14ef7a113ef517ec2bff179ecfd837"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5bb55de7635b9b20f716b59203757546"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5bb55de7635b9b20f716b59203757546">XRFDC_ADC_TDD_MODE0_OFFSET</a>&#160;&#160;&#160;0x068U</td></tr>
<tr class="memdesc:ga5bb55de7635b9b20f716b59203757546"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC TDD Mode 0 Configuration.  <a href="group___overview.html#ga5bb55de7635b9b20f716b59203757546">More...</a><br/></td></tr>
<tr class="separator:ga5bb55de7635b9b20f716b59203757546"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac433e22cac64099fccb17d6e6f61d7a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac433e22cac64099fccb17d6e6f61d7a1">XRFDC_TDD_MODE0_OFFSET</a>(X)&#160;&#160;&#160;((X == 0) ? <a class="el" href="group___overview.html#ga5bb55de7635b9b20f716b59203757546">XRFDC_ADC_TDD_MODE0_OFFSET</a> : <a class="el" href="group___overview.html#ga2f14ef7a113ef517ec2bff179ecfd837">XRFDC_DAC_TDD_MODE0_OFFSET</a>)</td></tr>
<tr class="memdesc:gac433e22cac64099fccb17d6e6f61d7a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC TDD Mode 0 Configuration.  <a href="group___overview.html#gac433e22cac64099fccb17d6e6f61d7a1">More...</a><br/></td></tr>
<tr class="separator:gac433e22cac64099fccb17d6e6f61d7a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0bbc470522469695707753b75a33e82d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0bbc470522469695707753b75a33e82d">XRFDC_ADC_MXR_CFG0_OFFSET</a>&#160;&#160;&#160;0x080U</td></tr>
<tr class="memdesc:ga0bbc470522469695707753b75a33e82d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC I channel mixer config Register.  <a href="group___overview.html#ga0bbc470522469695707753b75a33e82d">More...</a><br/></td></tr>
<tr class="separator:ga0bbc470522469695707753b75a33e82d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b75961d384cede50cca4d0fae50c623"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1b75961d384cede50cca4d0fae50c623">XRFDC_ADC_MXR_CFG1_OFFSET</a>&#160;&#160;&#160;0x084U</td></tr>
<tr class="memdesc:ga1b75961d384cede50cca4d0fae50c623"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Q channel mixer config Register.  <a href="group___overview.html#ga1b75961d384cede50cca4d0fae50c623">More...</a><br/></td></tr>
<tr class="separator:ga1b75961d384cede50cca4d0fae50c623"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ebb53254fa0a4439ca102bf98a2e60c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0ebb53254fa0a4439ca102bf98a2e60c">XRFDC_MXR_MODE_OFFSET</a>&#160;&#160;&#160;0x088U</td></tr>
<tr class="memdesc:ga0ebb53254fa0a4439ca102bf98a2e60c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC mixer mode Register.  <a href="group___overview.html#ga0ebb53254fa0a4439ca102bf98a2e60c">More...</a><br/></td></tr>
<tr class="separator:ga0ebb53254fa0a4439ca102bf98a2e60c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef4dde6d2ec4eb16f045d3a2400e4f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaef4dde6d2ec4eb16f045d3a2400e4f19">XRFDC_NCO_UPDT_OFFSET</a>&#160;&#160;&#160;0x08CU</td></tr>
<tr class="memdesc:gaef4dde6d2ec4eb16f045d3a2400e4f19"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC NCO Update mode Register.  <a href="group___overview.html#gaef4dde6d2ec4eb16f045d3a2400e4f19">More...</a><br/></td></tr>
<tr class="separator:gaef4dde6d2ec4eb16f045d3a2400e4f19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89750f53c53bf9b803b7f4b1e6baf47d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga89750f53c53bf9b803b7f4b1e6baf47d">XRFDC_NCO_RST_OFFSET</a>&#160;&#160;&#160;0x090U</td></tr>
<tr class="memdesc:ga89750f53c53bf9b803b7f4b1e6baf47d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC NCO Phase Reset Register.  <a href="group___overview.html#ga89750f53c53bf9b803b7f4b1e6baf47d">More...</a><br/></td></tr>
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<tr class="memitem:ga63604df4de7c15ca615a3556499b2260"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga63604df4de7c15ca615a3556499b2260">XRFDC_ADC_NCO_FQWD_UPP_OFFSET</a>&#160;&#160;&#160;0x094U</td></tr>
<tr class="memdesc:ga63604df4de7c15ca615a3556499b2260"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC NCO Frequency Word[47:32] Register.  <a href="group___overview.html#ga63604df4de7c15ca615a3556499b2260">More...</a><br/></td></tr>
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<tr class="memitem:ga1844134f5177f1ccec8eb9b11ab05e33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1844134f5177f1ccec8eb9b11ab05e33">XRFDC_ADC_NCO_FQWD_MID_OFFSET</a>&#160;&#160;&#160;0x098U</td></tr>
<tr class="memdesc:ga1844134f5177f1ccec8eb9b11ab05e33"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC NCO Frequency Word[31:16] Register.  <a href="group___overview.html#ga1844134f5177f1ccec8eb9b11ab05e33">More...</a><br/></td></tr>
<tr class="separator:ga1844134f5177f1ccec8eb9b11ab05e33"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1127c44e2f1c220a40704269365edf18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1127c44e2f1c220a40704269365edf18">XRFDC_ADC_NCO_FQWD_LOW_OFFSET</a>&#160;&#160;&#160;0x09CU</td></tr>
<tr class="memdesc:ga1127c44e2f1c220a40704269365edf18"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC NCO Frequency Word[15:0] Register.  <a href="group___overview.html#ga1127c44e2f1c220a40704269365edf18">More...</a><br/></td></tr>
<tr class="separator:ga1127c44e2f1c220a40704269365edf18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab08fa7dedfc69dccb3e9ff72b128df80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab08fa7dedfc69dccb3e9ff72b128df80">XRFDC_NCO_PHASE_UPP_OFFSET</a>&#160;&#160;&#160;0x0A0U</td></tr>
<tr class="memdesc:gab08fa7dedfc69dccb3e9ff72b128df80"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC NCO Phase[17:16] Register.  <a href="group___overview.html#gab08fa7dedfc69dccb3e9ff72b128df80">More...</a><br/></td></tr>
<tr class="separator:gab08fa7dedfc69dccb3e9ff72b128df80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98aa4878d8ddb1d681f33a1221185398"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga98aa4878d8ddb1d681f33a1221185398">XRFDC_NCO_PHASE_LOW_OFFSET</a>&#160;&#160;&#160;0x0A4U</td></tr>
<tr class="memdesc:ga98aa4878d8ddb1d681f33a1221185398"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC NCO Phase[15:0] Register.  <a href="group___overview.html#ga98aa4878d8ddb1d681f33a1221185398">More...</a><br/></td></tr>
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<tr class="memitem:gabf73e35ca19fb6ac80abbfcb30437674"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabf73e35ca19fb6ac80abbfcb30437674">XRFDC_ADC_NCO_PHASE_MOD_OFFSET</a>&#160;&#160;&#160;0x0A8U</td></tr>
<tr class="memdesc:gabf73e35ca19fb6ac80abbfcb30437674"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC NCO Phase Mode Register.  <a href="group___overview.html#gabf73e35ca19fb6ac80abbfcb30437674">More...</a><br/></td></tr>
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<tr class="memitem:ga56cc565194c7196b1eb05e3943ba46cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga56cc565194c7196b1eb05e3943ba46cd">XRFDC_QMC_UPDT_OFFSET</a>&#160;&#160;&#160;0x0C8U</td></tr>
<tr class="memdesc:ga56cc565194c7196b1eb05e3943ba46cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC QMC Update Mode Register.  <a href="group___overview.html#ga56cc565194c7196b1eb05e3943ba46cd">More...</a><br/></td></tr>
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<tr class="memitem:gafd6eb2446c86b9f8aab5878f7bcea9ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafd6eb2446c86b9f8aab5878f7bcea9ca">XRFDC_QMC_CFG_OFFSET</a>&#160;&#160;&#160;0x0CCU</td></tr>
<tr class="memdesc:gafd6eb2446c86b9f8aab5878f7bcea9ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC QMC Config Register.  <a href="group___overview.html#gafd6eb2446c86b9f8aab5878f7bcea9ca">More...</a><br/></td></tr>
<tr class="separator:gafd6eb2446c86b9f8aab5878f7bcea9ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf361c4825b276fc7fe5d86cdefaaf4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadf361c4825b276fc7fe5d86cdefaaf4c">XRFDC_QMC_OFF_OFFSET</a>&#160;&#160;&#160;0x0D0U</td></tr>
<tr class="memdesc:gadf361c4825b276fc7fe5d86cdefaaf4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC QMC Offset Correction Register.  <a href="group___overview.html#gadf361c4825b276fc7fe5d86cdefaaf4c">More...</a><br/></td></tr>
<tr class="separator:gadf361c4825b276fc7fe5d86cdefaaf4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga194b4b88e868b4265846fdd5f2477647"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga194b4b88e868b4265846fdd5f2477647">XRFDC_QMC_GAIN_OFFSET</a>&#160;&#160;&#160;0x0D4U</td></tr>
<tr class="memdesc:ga194b4b88e868b4265846fdd5f2477647"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC QMC Gain Correction Register.  <a href="group___overview.html#ga194b4b88e868b4265846fdd5f2477647">More...</a><br/></td></tr>
<tr class="separator:ga194b4b88e868b4265846fdd5f2477647"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3ae417057fbc9457e804936ec9004cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac3ae417057fbc9457e804936ec9004cc">XRFDC_QMC_PHASE_OFFSET</a>&#160;&#160;&#160;0x0D8U</td></tr>
<tr class="memdesc:gac3ae417057fbc9457e804936ec9004cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC QMC Phase Correction Register.  <a href="group___overview.html#gac3ae417057fbc9457e804936ec9004cc">More...</a><br/></td></tr>
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<tr class="memitem:ga8133892750e33d55d1f17ed50eee2314"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8133892750e33d55d1f17ed50eee2314">XRFDC_ADC_CRSE_DLY_UPDT_OFFSET</a>&#160;&#160;&#160;0x0DCU</td></tr>
<tr class="memdesc:ga8133892750e33d55d1f17ed50eee2314"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Coarse Delay Update Register.  <a href="group___overview.html#ga8133892750e33d55d1f17ed50eee2314">More...</a><br/></td></tr>
<tr class="separator:ga8133892750e33d55d1f17ed50eee2314"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff8002a03630bc9b752b4b34187404af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaff8002a03630bc9b752b4b34187404af">XRFDC_DAC_CRSE_DLY_UPDT_OFFSET</a>&#160;&#160;&#160;0x0E0U</td></tr>
<tr class="memdesc:gaff8002a03630bc9b752b4b34187404af"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Coarse Delay Update Register.  <a href="group___overview.html#gaff8002a03630bc9b752b4b34187404af">More...</a><br/></td></tr>
<tr class="separator:gaff8002a03630bc9b752b4b34187404af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae335d227c3e199508e6b0452ba3f6296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae335d227c3e199508e6b0452ba3f6296">XRFDC_ADC_CRSE_DLY_CFG_OFFSET</a>&#160;&#160;&#160;0x0E0U</td></tr>
<tr class="memdesc:gae335d227c3e199508e6b0452ba3f6296"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Coarse delay Config Register.  <a href="group___overview.html#gae335d227c3e199508e6b0452ba3f6296">More...</a><br/></td></tr>
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<tr class="memitem:gae784e08ee24ab9bba6fe122bd1b00119"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae784e08ee24ab9bba6fe122bd1b00119">XRFDC_DAC_CRSE_DLY_CFG_OFFSET</a>&#160;&#160;&#160;0x0DCU</td></tr>
<tr class="memdesc:gae784e08ee24ab9bba6fe122bd1b00119"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Coarse delay Config Register.  <a href="group___overview.html#gae784e08ee24ab9bba6fe122bd1b00119">More...</a><br/></td></tr>
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<tr class="memitem:gadcc2fbf2c2eb8fa22a74c70694bf87b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadcc2fbf2c2eb8fa22a74c70694bf87b6">XRFDC_ADC_DAT_SCAL_CFG_OFFSET</a>&#160;&#160;&#160;0x0E4U</td></tr>
<tr class="memdesc:gadcc2fbf2c2eb8fa22a74c70694bf87b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Data Scaling Config Register.  <a href="group___overview.html#gadcc2fbf2c2eb8fa22a74c70694bf87b6">More...</a><br/></td></tr>
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<tr class="memitem:ga4594c23883f6356a94c447a638288575"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4594c23883f6356a94c447a638288575">XRFDC_ADC_SWITCH_MATRX_OFFSET</a>&#160;&#160;&#160;0x0E8U</td></tr>
<tr class="memdesc:ga4594c23883f6356a94c447a638288575"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Switch Matrix Config Register.  <a href="group___overview.html#ga4594c23883f6356a94c447a638288575">More...</a><br/></td></tr>
<tr class="separator:ga4594c23883f6356a94c447a638288575"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga618e1be96c3d091ed26b9186c5da8d50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga618e1be96c3d091ed26b9186c5da8d50">XRFDC_ADC_TRSHD0_CFG_OFFSET</a>&#160;&#160;&#160;0x0ECU</td></tr>
<tr class="memdesc:ga618e1be96c3d091ed26b9186c5da8d50"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold0 Config Register.  <a href="group___overview.html#ga618e1be96c3d091ed26b9186c5da8d50">More...</a><br/></td></tr>
<tr class="separator:ga618e1be96c3d091ed26b9186c5da8d50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc3782c386a46e229271fce06ebe2b94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafc3782c386a46e229271fce06ebe2b94">XRFDC_ADC_TRSHD0_AVG_UP_OFFSET</a>&#160;&#160;&#160;0x0F0U</td></tr>
<tr class="memdesc:gafc3782c386a46e229271fce06ebe2b94"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold0 Average[31:16] Register.  <a href="group___overview.html#gafc3782c386a46e229271fce06ebe2b94">More...</a><br/></td></tr>
<tr class="separator:gafc3782c386a46e229271fce06ebe2b94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fb61cf86024132b24efbde6924c1024"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1fb61cf86024132b24efbde6924c1024">XRFDC_ADC_TRSHD0_AVG_LO_OFFSET</a>&#160;&#160;&#160;0x0F4U</td></tr>
<tr class="memdesc:ga1fb61cf86024132b24efbde6924c1024"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold0 Average[15:0] Register.  <a href="group___overview.html#ga1fb61cf86024132b24efbde6924c1024">More...</a><br/></td></tr>
<tr class="separator:ga1fb61cf86024132b24efbde6924c1024"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceb9bd0439d92cceac590d9ea9b1c1bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaceb9bd0439d92cceac590d9ea9b1c1bf">XRFDC_ADC_TRSHD0_UNDER_OFFSET</a>&#160;&#160;&#160;0x0F8U</td></tr>
<tr class="memdesc:gaceb9bd0439d92cceac590d9ea9b1c1bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold0 Under Threshold Register.  <a href="group___overview.html#gaceb9bd0439d92cceac590d9ea9b1c1bf">More...</a><br/></td></tr>
<tr class="separator:gaceb9bd0439d92cceac590d9ea9b1c1bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d852a948038475db38f73493268e1a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d852a948038475db38f73493268e1a0">XRFDC_ADC_TRSHD0_OVER_OFFSET</a>&#160;&#160;&#160;0x0FCU</td></tr>
<tr class="memdesc:ga2d852a948038475db38f73493268e1a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold0 Over Threshold Register.  <a href="group___overview.html#ga2d852a948038475db38f73493268e1a0">More...</a><br/></td></tr>
<tr class="separator:ga2d852a948038475db38f73493268e1a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9c1f8e41d63cbb570c6ca8e4dd2602d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad9c1f8e41d63cbb570c6ca8e4dd2602d">XRFDC_ADC_TRSHD1_CFG_OFFSET</a>&#160;&#160;&#160;0x100U</td></tr>
<tr class="memdesc:gad9c1f8e41d63cbb570c6ca8e4dd2602d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold1 Config Register.  <a href="group___overview.html#gad9c1f8e41d63cbb570c6ca8e4dd2602d">More...</a><br/></td></tr>
<tr class="separator:gad9c1f8e41d63cbb570c6ca8e4dd2602d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2ab09d8237ffb91f5c064a5fe5c9c79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab2ab09d8237ffb91f5c064a5fe5c9c79">XRFDC_ADC_TRSHD1_AVG_UP_OFFSET</a>&#160;&#160;&#160;0x104U</td></tr>
<tr class="memdesc:gab2ab09d8237ffb91f5c064a5fe5c9c79"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold1 Average[31:16] Register.  <a href="group___overview.html#gab2ab09d8237ffb91f5c064a5fe5c9c79">More...</a><br/></td></tr>
<tr class="separator:gab2ab09d8237ffb91f5c064a5fe5c9c79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f44d7132eab56d77b666b95ebaa5974"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9f44d7132eab56d77b666b95ebaa5974">XRFDC_ADC_TRSHD1_AVG_LO_OFFSET</a>&#160;&#160;&#160;0x108U</td></tr>
<tr class="memdesc:ga9f44d7132eab56d77b666b95ebaa5974"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold1 Average[15:0] Register.  <a href="group___overview.html#ga9f44d7132eab56d77b666b95ebaa5974">More...</a><br/></td></tr>
<tr class="separator:ga9f44d7132eab56d77b666b95ebaa5974"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c94834dee093323be3e7cf0bd66a409"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5c94834dee093323be3e7cf0bd66a409">XRFDC_ADC_TRSHD1_UNDER_OFFSET</a>&#160;&#160;&#160;0x10CU</td></tr>
<tr class="memdesc:ga5c94834dee093323be3e7cf0bd66a409"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold1 Under Threshold Register.  <a href="group___overview.html#ga5c94834dee093323be3e7cf0bd66a409">More...</a><br/></td></tr>
<tr class="separator:ga5c94834dee093323be3e7cf0bd66a409"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3085d89c7943e580f3457da407e202f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3085d89c7943e580f3457da407e202f5">XRFDC_ADC_TRSHD1_OVER_OFFSET</a>&#160;&#160;&#160;0x110U</td></tr>
<tr class="memdesc:ga3085d89c7943e580f3457da407e202f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Threshold1 Over Threshold Register.  <a href="group___overview.html#ga3085d89c7943e580f3457da407e202f5">More...</a><br/></td></tr>
<tr class="separator:ga3085d89c7943e580f3457da407e202f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34a11c34bb81c3124539cf8b7d54da5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga34a11c34bb81c3124539cf8b7d54da5d">XRFDC_ADC_FEND_DAT_CRL_OFFSET</a>&#160;&#160;&#160;0x140U</td></tr>
<tr class="memdesc:ga34a11c34bb81c3124539cf8b7d54da5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Front end Data Control Register.  <a href="group___overview.html#ga34a11c34bb81c3124539cf8b7d54da5d">More...</a><br/></td></tr>
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<tr class="memitem:gacaa9a2ac591c8000d815f63e881d00f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacaa9a2ac591c8000d815f63e881d00f1">XRFDC_ADC_TI_DCB_CRL0_OFFSET</a>&#160;&#160;&#160;0x144U</td></tr>
<tr class="memdesc:gacaa9a2ac591c8000d815f63e881d00f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time Interleaved digital correction block gain control0 Register.  <a href="group___overview.html#gacaa9a2ac591c8000d815f63e881d00f1">More...</a><br/></td></tr>
<tr class="separator:gacaa9a2ac591c8000d815f63e881d00f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac98e45d6a55cf51119a9f0a3cd93e348"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac98e45d6a55cf51119a9f0a3cd93e348">XRFDC_ADC_TI_DCB_CRL1_OFFSET</a>&#160;&#160;&#160;0x148U</td></tr>
<tr class="memdesc:gac98e45d6a55cf51119a9f0a3cd93e348"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time Interleaved digital correction block gain control1 Register.  <a href="group___overview.html#gac98e45d6a55cf51119a9f0a3cd93e348">More...</a><br/></td></tr>
<tr class="separator:gac98e45d6a55cf51119a9f0a3cd93e348"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga833f68798597f327180f9a55725ced8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga833f68798597f327180f9a55725ced8e">XRFDC_ADC_TI_DCB_CRL2_OFFSET</a>&#160;&#160;&#160;0x14CU</td></tr>
<tr class="memdesc:ga833f68798597f327180f9a55725ced8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time Interleaved digital correction block gain control2 Register.  <a href="group___overview.html#ga833f68798597f327180f9a55725ced8e">More...</a><br/></td></tr>
<tr class="separator:ga833f68798597f327180f9a55725ced8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb2e0265fbc3b6dbe3218eb87cb34de1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabb2e0265fbc3b6dbe3218eb87cb34de1">XRFDC_ADC_TI_DCB_CRL3_OFFSET</a>&#160;&#160;&#160;0x150U</td></tr>
<tr class="memdesc:gabb2e0265fbc3b6dbe3218eb87cb34de1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time Interleaved digital correction block gain control3 Register.  <a href="group___overview.html#gabb2e0265fbc3b6dbe3218eb87cb34de1">More...</a><br/></td></tr>
<tr class="separator:gabb2e0265fbc3b6dbe3218eb87cb34de1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92a974ea3a027dab8edf9a752317f182"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga92a974ea3a027dab8edf9a752317f182">XRFDC_ADC_TI_TISK_CRL0_OFFSET</a>&#160;&#160;&#160;0x154U</td></tr>
<tr class="memdesc:ga92a974ea3a027dab8edf9a752317f182"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits0 Register.  <a href="group___overview.html#ga92a974ea3a027dab8edf9a752317f182">More...</a><br/></td></tr>
<tr class="separator:ga92a974ea3a027dab8edf9a752317f182"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ad46a818c4133624a1cdcc45400d932"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8ad46a818c4133624a1cdcc45400d932">XRFDC_DAC_MC_CFG0_OFFSET</a>&#160;&#160;&#160;0x1C4U</td></tr>
<tr class="memdesc:ga8ad46a818c4133624a1cdcc45400d932"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Configuration data for DAC Analog.  <a href="group___overview.html#ga8ad46a818c4133624a1cdcc45400d932">More...</a><br/></td></tr>
<tr class="separator:ga8ad46a818c4133624a1cdcc45400d932"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a58a307c4ad73f6da874f4ff88f786a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a58a307c4ad73f6da874f4ff88f786a">XRFDC_ADC_TI_TISK_CRL1_OFFSET</a>&#160;&#160;&#160;0x158U</td></tr>
<tr class="memdesc:ga0a58a307c4ad73f6da874f4ff88f786a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits1 Register.  <a href="group___overview.html#ga0a58a307c4ad73f6da874f4ff88f786a">More...</a><br/></td></tr>
<tr class="separator:ga0a58a307c4ad73f6da874f4ff88f786a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83a421b462df8000e86125f3251bfbe1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga83a421b462df8000e86125f3251bfbe1">XRFDC_ADC_TI_TISK_CRL2_OFFSET</a>&#160;&#160;&#160;0x15CU</td></tr>
<tr class="memdesc:ga83a421b462df8000e86125f3251bfbe1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits2 Register.  <a href="group___overview.html#ga83a421b462df8000e86125f3251bfbe1">More...</a><br/></td></tr>
<tr class="separator:ga83a421b462df8000e86125f3251bfbe1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dc9c1df0ec6589af4829817a8591a74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0dc9c1df0ec6589af4829817a8591a74">XRFDC_ADC_TI_TISK_CRL3_OFFSET</a>&#160;&#160;&#160;0x160U</td></tr>
<tr class="memdesc:ga0dc9c1df0ec6589af4829817a8591a74"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits3 Register.  <a href="group___overview.html#ga0dc9c1df0ec6589af4829817a8591a74">More...</a><br/></td></tr>
<tr class="separator:ga0dc9c1df0ec6589af4829817a8591a74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad24b75c24ec043f409e8219abab7b262"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad24b75c24ec043f409e8219abab7b262">XRFDC_ADC_TI_TISK_CRL4_OFFSET</a>&#160;&#160;&#160;0x164U</td></tr>
<tr class="memdesc:gad24b75c24ec043f409e8219abab7b262"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits4 Register.  <a href="group___overview.html#gad24b75c24ec043f409e8219abab7b262">More...</a><br/></td></tr>
<tr class="separator:gad24b75c24ec043f409e8219abab7b262"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad820c60054575e4efe87c904dc2ce568"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad820c60054575e4efe87c904dc2ce568">XRFDC_ADC_TI_TISK_CRL5_OFFSET</a>&#160;&#160;&#160;0x168U</td></tr>
<tr class="memdesc:gad820c60054575e4efe87c904dc2ce568"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew correction control bits5 Register (Gen 3 only)  <a href="group___overview.html#gad820c60054575e4efe87c904dc2ce568">More...</a><br/></td></tr>
<tr class="separator:gad820c60054575e4efe87c904dc2ce568"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf3e5b06abc8d03f292ca3d902234fe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabf3e5b06abc8d03f292ca3d902234fe5">XRFDC_ADC_TI_TISK_DAC0_OFFSET</a>&#160;&#160;&#160;0x168U</td></tr>
<tr class="memdesc:gabf3e5b06abc8d03f292ca3d902234fe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch0 Register(Below Gen 3)  <a href="group___overview.html#gabf3e5b06abc8d03f292ca3d902234fe5">More...</a><br/></td></tr>
<tr class="separator:gabf3e5b06abc8d03f292ca3d902234fe5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga831959bfe4c483d08cb77623f1f13edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga831959bfe4c483d08cb77623f1f13edd">XRFDC_ADC_TI_TISK_DAC1_OFFSET</a>&#160;&#160;&#160;0x16CU</td></tr>
<tr class="memdesc:ga831959bfe4c483d08cb77623f1f13edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch1 Register.  <a href="group___overview.html#ga831959bfe4c483d08cb77623f1f13edd">More...</a><br/></td></tr>
<tr class="separator:ga831959bfe4c483d08cb77623f1f13edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6148f6116c9e220d2751b771326798a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6148f6116c9e220d2751b771326798a6">XRFDC_ADC_TI_TISK_DAC2_OFFSET</a>&#160;&#160;&#160;0x170U</td></tr>
<tr class="memdesc:ga6148f6116c9e220d2751b771326798a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch2 Register.  <a href="group___overview.html#ga6148f6116c9e220d2751b771326798a6">More...</a><br/></td></tr>
<tr class="separator:ga6148f6116c9e220d2751b771326798a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga951a4a7cf568a41b10e143d8da78ec21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga951a4a7cf568a41b10e143d8da78ec21">XRFDC_ADC_TI_TISK_DAC3_OFFSET</a>&#160;&#160;&#160;0x174U</td></tr>
<tr class="memdesc:ga951a4a7cf568a41b10e143d8da78ec21"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch3 Register.  <a href="group___overview.html#ga951a4a7cf568a41b10e143d8da78ec21">More...</a><br/></td></tr>
<tr class="separator:ga951a4a7cf568a41b10e143d8da78ec21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20348181af19eb3ac2ac6d49dc06834c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga20348181af19eb3ac2ac6d49dc06834c">XRFDC_ADC_TI_TISK_DACP0_OFFSET</a>&#160;&#160;&#160;0x178U</td></tr>
<tr class="memdesc:ga20348181af19eb3ac2ac6d49dc06834c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch0 Register.  <a href="group___overview.html#ga20348181af19eb3ac2ac6d49dc06834c">More...</a><br/></td></tr>
<tr class="separator:ga20348181af19eb3ac2ac6d49dc06834c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85877361f037c79c8c2f71bb49e8188b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga85877361f037c79c8c2f71bb49e8188b">XRFDC_ADC_TI_TISK_DACP1_OFFSET</a>&#160;&#160;&#160;0x17CU</td></tr>
<tr class="memdesc:ga85877361f037c79c8c2f71bb49e8188b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch1 Register.  <a href="group___overview.html#ga85877361f037c79c8c2f71bb49e8188b">More...</a><br/></td></tr>
<tr class="separator:ga85877361f037c79c8c2f71bb49e8188b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf74869e0ed59ad127a80d1794309a731"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf74869e0ed59ad127a80d1794309a731">XRFDC_ADC_TI_TISK_DACP2_OFFSET</a>&#160;&#160;&#160;0x180U</td></tr>
<tr class="memdesc:gaf74869e0ed59ad127a80d1794309a731"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch2 Register.  <a href="group___overview.html#gaf74869e0ed59ad127a80d1794309a731">More...</a><br/></td></tr>
<tr class="separator:gaf74869e0ed59ad127a80d1794309a731"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga368bfc98cb9a6108f075a83f55e29cb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga368bfc98cb9a6108f075a83f55e29cb7">XRFDC_ADC_TI_TISK_DACP3_OFFSET</a>&#160;&#160;&#160;0x184U</td></tr>
<tr class="memdesc:ga368bfc98cb9a6108f075a83f55e29cb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Time skew DAC cal code of subadc ch3 Register.  <a href="group___overview.html#ga368bfc98cb9a6108f075a83f55e29cb7">More...</a><br/></td></tr>
<tr class="separator:ga368bfc98cb9a6108f075a83f55e29cb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d84e90d9be8f94cfb18233a69eadf98"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5d84e90d9be8f94cfb18233a69eadf98">XRFDC_DATA_SCALER_OFFSET</a>&#160;&#160;&#160;0x190U</td></tr>
<tr class="memdesc:ga5d84e90d9be8f94cfb18233a69eadf98"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Data Scaler Register.  <a href="group___overview.html#ga5d84e90d9be8f94cfb18233a69eadf98">More...</a><br/></td></tr>
<tr class="separator:ga5d84e90d9be8f94cfb18233a69eadf98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf902b85aa68ccc789d4602179fef61ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf902b85aa68ccc789d4602179fef61ad">XRFDC_DAC_VOP_CTRL_OFFSET</a>&#160;&#160;&#160;0x198U</td></tr>
<tr class="memdesc:gaf902b85aa68ccc789d4602179fef61ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC variable output power control Register.  <a href="group___overview.html#gaf902b85aa68ccc789d4602179fef61ad">More...</a><br/></td></tr>
<tr class="separator:gaf902b85aa68ccc789d4602179fef61ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf58758e5a7e4d0cdcbef777c033202b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf58758e5a7e4d0cdcbef777c033202b1">XRFDC_ADC0_SUBDRP_ADDR_OFFSET</a>&#160;&#160;&#160;0x198U</td></tr>
<tr class="memdesc:gaf58758e5a7e4d0cdcbef777c033202b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0, sub-drp address of target Register  <a href="group___overview.html#gaf58758e5a7e4d0cdcbef777c033202b1">More...</a><br/></td></tr>
<tr class="separator:gaf58758e5a7e4d0cdcbef777c033202b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf9d29ac3311c4a2a673f8afc773610f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacf9d29ac3311c4a2a673f8afc773610f">XRFDC_ADC0_SUBDRP_DAT_OFFSET</a>&#160;&#160;&#160;0x19CU</td></tr>
<tr class="memdesc:gacf9d29ac3311c4a2a673f8afc773610f"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0, sub-drp data of target Register  <a href="group___overview.html#gacf9d29ac3311c4a2a673f8afc773610f">More...</a><br/></td></tr>
<tr class="separator:gacf9d29ac3311c4a2a673f8afc773610f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2f8277f13b756250b604fd42453d1d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad2f8277f13b756250b604fd42453d1d6">XRFDC_ADC1_SUBDRP_ADDR_OFFSET</a>&#160;&#160;&#160;0x1A0U</td></tr>
<tr class="memdesc:gad2f8277f13b756250b604fd42453d1d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1, sub-drp address of target Register  <a href="group___overview.html#gad2f8277f13b756250b604fd42453d1d6">More...</a><br/></td></tr>
<tr class="separator:gad2f8277f13b756250b604fd42453d1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed2f1d6d6a61add79f48a6434a26a5f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaed2f1d6d6a61add79f48a6434a26a5f6">XRFDC_ADC1_SUBDRP_DAT_OFFSET</a>&#160;&#160;&#160;0x1A4U</td></tr>
<tr class="memdesc:gaed2f1d6d6a61add79f48a6434a26a5f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1, sub-drp data of target Register  <a href="group___overview.html#gaed2f1d6d6a61add79f48a6434a26a5f6">More...</a><br/></td></tr>
<tr class="separator:gaed2f1d6d6a61add79f48a6434a26a5f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae776186e5723ee23daf435b30da7ef0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae776186e5723ee23daf435b30da7ef0c">XRFDC_ADC2_SUBDRP_ADDR_OFFSET</a>&#160;&#160;&#160;0x1A8U</td></tr>
<tr class="memdesc:gae776186e5723ee23daf435b30da7ef0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2, sub-drp address of target Register  <a href="group___overview.html#gae776186e5723ee23daf435b30da7ef0c">More...</a><br/></td></tr>
<tr class="separator:gae776186e5723ee23daf435b30da7ef0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed1425b39e2b6a47c40e32ac337db699"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaed1425b39e2b6a47c40e32ac337db699">XRFDC_ADC2_SUBDRP_DAT_OFFSET</a>&#160;&#160;&#160;0x1ACU</td></tr>
<tr class="memdesc:gaed1425b39e2b6a47c40e32ac337db699"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2, sub-drp data of target Register  <a href="group___overview.html#gaed1425b39e2b6a47c40e32ac337db699">More...</a><br/></td></tr>
<tr class="separator:gaed1425b39e2b6a47c40e32ac337db699"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd0735c2bbd0854179362bd70c355658"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafd0735c2bbd0854179362bd70c355658">XRFDC_ADC3_SUBDRP_ADDR_OFFSET</a>&#160;&#160;&#160;0x1B0U</td></tr>
<tr class="memdesc:gafd0735c2bbd0854179362bd70c355658"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3, sub-drp address of target Register  <a href="group___overview.html#gafd0735c2bbd0854179362bd70c355658">More...</a><br/></td></tr>
<tr class="separator:gafd0735c2bbd0854179362bd70c355658"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7035f446284f27a9faf2c0ea1c3e9a71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7035f446284f27a9faf2c0ea1c3e9a71">XRFDC_ADC3_SUBDRP_DAT_OFFSET</a>&#160;&#160;&#160;0x1B4U</td></tr>
<tr class="memdesc:ga7035f446284f27a9faf2c0ea1c3e9a71"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3, sub-drp data of target Register  <a href="group___overview.html#ga7035f446284f27a9faf2c0ea1c3e9a71">More...</a><br/></td></tr>
<tr class="separator:ga7035f446284f27a9faf2c0ea1c3e9a71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ba67f71fca4764e31413f3f3a3833ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0ba67f71fca4764e31413f3f3a3833ae">XRFDC_ADC_RX_MC_PWRDWN_OFFSET</a>&#160;&#160;&#160;0x1C0U</td></tr>
<tr class="memdesc:ga0ba67f71fca4764e31413f3f3a3833ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Static configuration bits for ADC(RX) analog Register.  <a href="group___overview.html#ga0ba67f71fca4764e31413f3f3a3833ae">More...</a><br/></td></tr>
<tr class="separator:ga0ba67f71fca4764e31413f3f3a3833ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ee1b46f3d577063eb34450e58046ae3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8ee1b46f3d577063eb34450e58046ae3">XRFDC_ADC_DAC_MC_CFG0_OFFSET</a>&#160;&#160;&#160;0x1C4U</td></tr>
<tr class="memdesc:ga8ee1b46f3d577063eb34450e58046ae3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC Static configuration bits for ADC/DAC analog Register.  <a href="group___overview.html#ga8ee1b46f3d577063eb34450e58046ae3">More...</a><br/></td></tr>
<tr class="separator:ga8ee1b46f3d577063eb34450e58046ae3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fc76441cb561c9b1a5cfe45c19a3ea9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7fc76441cb561c9b1a5cfe45c19a3ea9">XRFDC_ADC_DAC_MC_CFG1_OFFSET</a>&#160;&#160;&#160;0x1C8U</td></tr>
<tr class="memdesc:ga7fc76441cb561c9b1a5cfe45c19a3ea9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC Static configuration bits for ADC/DAC analog Register.  <a href="group___overview.html#ga7fc76441cb561c9b1a5cfe45c19a3ea9">More...</a><br/></td></tr>
<tr class="separator:ga7fc76441cb561c9b1a5cfe45c19a3ea9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ee17f4d76b2f205d1498847f4e0cfa3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7ee17f4d76b2f205d1498847f4e0cfa3">XRFDC_ADC_DAC_MC_CFG2_OFFSET</a>&#160;&#160;&#160;0x1CCU</td></tr>
<tr class="memdesc:ga7ee17f4d76b2f205d1498847f4e0cfa3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC/DAC Static configuration bits for ADC/DAC analog Register.  <a href="group___overview.html#ga7ee17f4d76b2f205d1498847f4e0cfa3">More...</a><br/></td></tr>
<tr class="separator:ga7ee17f4d76b2f205d1498847f4e0cfa3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga254695ad1dfc8e8feae3086f391852f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga254695ad1dfc8e8feae3086f391852f0">XRFDC_DAC_MC_CFG3_OFFSET</a>&#160;&#160;&#160;0x1D0U</td></tr>
<tr class="memdesc:ga254695ad1dfc8e8feae3086f391852f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Static configuration bits for DAC analog Register.  <a href="group___overview.html#ga254695ad1dfc8e8feae3086f391852f0">More...</a><br/></td></tr>
<tr class="separator:ga254695ad1dfc8e8feae3086f391852f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84b7b15491770ceaf1a587bb0b4e7d76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga84b7b15491770ceaf1a587bb0b4e7d76">XRFDC_ADC_RXPR_MC_CFG0_OFFSET</a>&#160;&#160;&#160;0x1D0U</td></tr>
<tr class="memdesc:ga84b7b15491770ceaf1a587bb0b4e7d76"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC RX Pair static Configuration Register.  <a href="group___overview.html#ga84b7b15491770ceaf1a587bb0b4e7d76">More...</a><br/></td></tr>
<tr class="separator:ga84b7b15491770ceaf1a587bb0b4e7d76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48f47e8bc1b303ca30865495626d070e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga48f47e8bc1b303ca30865495626d070e">XRFDC_ADC_RXPR_MC_CFG1_OFFSET</a>&#160;&#160;&#160;0x1D4U</td></tr>
<tr class="memdesc:ga48f47e8bc1b303ca30865495626d070e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC RX Pair static Configuration Register.  <a href="group___overview.html#ga48f47e8bc1b303ca30865495626d070e">More...</a><br/></td></tr>
<tr class="separator:ga48f47e8bc1b303ca30865495626d070e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa9b9cd24665a2a7f0c4c10358968e616"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa9b9cd24665a2a7f0c4c10358968e616">XRFDC_ADC_TI_DCBSTS0_BG_OFFSET</a>&#160;&#160;&#160;0x200U</td></tr>
<tr class="memdesc:gaa9b9cd24665a2a7f0c4c10358968e616"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status0 BG Register.  <a href="group___overview.html#gaa9b9cd24665a2a7f0c4c10358968e616">More...</a><br/></td></tr>
<tr class="separator:gaa9b9cd24665a2a7f0c4c10358968e616"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8960c84f9cb08826475301a3aa8321b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae8960c84f9cb08826475301a3aa8321b">XRFDC_ADC_TI_DCBSTS0_FG_OFFSET</a>&#160;&#160;&#160;0x204U</td></tr>
<tr class="memdesc:gae8960c84f9cb08826475301a3aa8321b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status0 FG Register.  <a href="group___overview.html#gae8960c84f9cb08826475301a3aa8321b">More...</a><br/></td></tr>
<tr class="separator:gae8960c84f9cb08826475301a3aa8321b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3591a0a28304e5c255b0b579424c72f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3591a0a28304e5c255b0b579424c72f6">XRFDC_ADC_TI_DCBSTS1_BG_OFFSET</a>&#160;&#160;&#160;0x208U</td></tr>
<tr class="memdesc:ga3591a0a28304e5c255b0b579424c72f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status1 BG Register.  <a href="group___overview.html#ga3591a0a28304e5c255b0b579424c72f6">More...</a><br/></td></tr>
<tr class="separator:ga3591a0a28304e5c255b0b579424c72f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1494617f5af8c1e1640639d46b7356d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae1494617f5af8c1e1640639d46b7356d">XRFDC_ADC_TI_DCBSTS1_FG_OFFSET</a>&#160;&#160;&#160;0x20CU</td></tr>
<tr class="memdesc:gae1494617f5af8c1e1640639d46b7356d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status1 FG Register.  <a href="group___overview.html#gae1494617f5af8c1e1640639d46b7356d">More...</a><br/></td></tr>
<tr class="separator:gae1494617f5af8c1e1640639d46b7356d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87c370ecdd9018569eaec4122978543a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga87c370ecdd9018569eaec4122978543a">XRFDC_ADC_TI_DCBSTS2_BG_OFFSET</a>&#160;&#160;&#160;0x210U</td></tr>
<tr class="memdesc:ga87c370ecdd9018569eaec4122978543a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status2 BG Register.  <a href="group___overview.html#ga87c370ecdd9018569eaec4122978543a">More...</a><br/></td></tr>
<tr class="separator:ga87c370ecdd9018569eaec4122978543a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95679cb1d9980374f8d1ca9715ad4e79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga95679cb1d9980374f8d1ca9715ad4e79">XRFDC_ADC_TI_DCBSTS2_FG_OFFSET</a>&#160;&#160;&#160;0x214U</td></tr>
<tr class="memdesc:ga95679cb1d9980374f8d1ca9715ad4e79"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status2 FG Register.  <a href="group___overview.html#ga95679cb1d9980374f8d1ca9715ad4e79">More...</a><br/></td></tr>
<tr class="separator:ga95679cb1d9980374f8d1ca9715ad4e79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d0f75c08ebb278f12d58237fae8f268"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0d0f75c08ebb278f12d58237fae8f268">XRFDC_ADC_TI_DCBSTS3_BG_OFFSET</a>&#160;&#160;&#160;0x218U</td></tr>
<tr class="memdesc:ga0d0f75c08ebb278f12d58237fae8f268"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status3 BG Register.  <a href="group___overview.html#ga0d0f75c08ebb278f12d58237fae8f268">More...</a><br/></td></tr>
<tr class="separator:ga0d0f75c08ebb278f12d58237fae8f268"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22e0c5475801baa8ab27e2585efe73a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga22e0c5475801baa8ab27e2585efe73a1">XRFDC_ADC_TI_DCBSTS3_FG_OFFSET</a>&#160;&#160;&#160;0x21CU</td></tr>
<tr class="memdesc:ga22e0c5475801baa8ab27e2585efe73a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status3 FG Register.  <a href="group___overview.html#ga22e0c5475801baa8ab27e2585efe73a1">More...</a><br/></td></tr>
<tr class="separator:ga22e0c5475801baa8ab27e2585efe73a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0683daf3842e55947f2590409c7689c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0683daf3842e55947f2590409c7689c8">XRFDC_ADC_TI_DCBSTS4_MB_OFFSET</a>&#160;&#160;&#160;0x220U</td></tr>
<tr class="memdesc:ga0683daf3842e55947f2590409c7689c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status4 MSB Register.  <a href="group___overview.html#ga0683daf3842e55947f2590409c7689c8">More...</a><br/></td></tr>
<tr class="separator:ga0683daf3842e55947f2590409c7689c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae41a399d2c1545340dbf878e7dd46d6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae41a399d2c1545340dbf878e7dd46d6b">XRFDC_ADC_TI_DCBSTS4_LB_OFFSET</a>&#160;&#160;&#160;0x224U</td></tr>
<tr class="memdesc:gae41a399d2c1545340dbf878e7dd46d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status4 LSB Register.  <a href="group___overview.html#gae41a399d2c1545340dbf878e7dd46d6b">More...</a><br/></td></tr>
<tr class="separator:gae41a399d2c1545340dbf878e7dd46d6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf789871a8733c7ea34d8982863ded76b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf789871a8733c7ea34d8982863ded76b">XRFDC_ADC_TI_DCBSTS5_MB_OFFSET</a>&#160;&#160;&#160;0x228U</td></tr>
<tr class="memdesc:gaf789871a8733c7ea34d8982863ded76b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status5 MSB Register.  <a href="group___overview.html#gaf789871a8733c7ea34d8982863ded76b">More...</a><br/></td></tr>
<tr class="separator:gaf789871a8733c7ea34d8982863ded76b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb32c778cebfd78ef44d6a12e0450795"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaeb32c778cebfd78ef44d6a12e0450795">XRFDC_ADC_TI_DCBSTS5_LB_OFFSET</a>&#160;&#160;&#160;0x22CU</td></tr>
<tr class="memdesc:gaeb32c778cebfd78ef44d6a12e0450795"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status5 LSB Register.  <a href="group___overview.html#gaeb32c778cebfd78ef44d6a12e0450795">More...</a><br/></td></tr>
<tr class="separator:gaeb32c778cebfd78ef44d6a12e0450795"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga336b625d54c7e8b1f62d6e6bf84f2400"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga336b625d54c7e8b1f62d6e6bf84f2400">XRFDC_ADC_TI_DCBSTS6_MB_OFFSET</a>&#160;&#160;&#160;0x230U</td></tr>
<tr class="memdesc:ga336b625d54c7e8b1f62d6e6bf84f2400"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status6 MSB Register.  <a href="group___overview.html#ga336b625d54c7e8b1f62d6e6bf84f2400">More...</a><br/></td></tr>
<tr class="separator:ga336b625d54c7e8b1f62d6e6bf84f2400"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e95d6c8b0296aaf4e6c52915f900d1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5e95d6c8b0296aaf4e6c52915f900d1c">XRFDC_ADC_TI_DCBSTS6_LB_OFFSET</a>&#160;&#160;&#160;0x234U</td></tr>
<tr class="memdesc:ga5e95d6c8b0296aaf4e6c52915f900d1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status6 LSB Register.  <a href="group___overview.html#ga5e95d6c8b0296aaf4e6c52915f900d1c">More...</a><br/></td></tr>
<tr class="separator:ga5e95d6c8b0296aaf4e6c52915f900d1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21c0ca01de997d435f2b2f5f25c0905a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga21c0ca01de997d435f2b2f5f25c0905a">XRFDC_ADC_TI_DCBSTS7_MB_OFFSET</a>&#160;&#160;&#160;0x238U</td></tr>
<tr class="memdesc:ga21c0ca01de997d435f2b2f5f25c0905a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status7 MSB Register.  <a href="group___overview.html#ga21c0ca01de997d435f2b2f5f25c0905a">More...</a><br/></td></tr>
<tr class="separator:ga21c0ca01de997d435f2b2f5f25c0905a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72749b4926ec17562b963c5cda563329"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga72749b4926ec17562b963c5cda563329">XRFDC_ADC_TI_DCBSTS7_LB_OFFSET</a>&#160;&#160;&#160;0x23CU</td></tr>
<tr class="memdesc:ga72749b4926ec17562b963c5cda563329"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DCB Status7 LSB Register.  <a href="group___overview.html#ga72749b4926ec17562b963c5cda563329">More...</a><br/></td></tr>
<tr class="separator:ga72749b4926ec17562b963c5cda563329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad42ad3e3a54b69328ce1d2f23e73ff99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad42ad3e3a54b69328ce1d2f23e73ff99">XRFDC_DSA_UPDT_OFFSET</a>&#160;&#160;&#160;0x254U</td></tr>
<tr class="memdesc:gad42ad3e3a54b69328ce1d2f23e73ff99"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DSA Update Trigger REgister.  <a href="group___overview.html#gad42ad3e3a54b69328ce1d2f23e73ff99">More...</a><br/></td></tr>
<tr class="separator:gad42ad3e3a54b69328ce1d2f23e73ff99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad639e19f23a2fcf293866343cb0a14b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad639e19f23a2fcf293866343cb0a14b5">XRFDC_ADC_FIFO_LTNCY_LB_OFFSET</a>&#160;&#160;&#160;0x280U</td></tr>
<tr class="memdesc:gad639e19f23a2fcf293866343cb0a14b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Latency measurement LSB Register.  <a href="group___overview.html#gad639e19f23a2fcf293866343cb0a14b5">More...</a><br/></td></tr>
<tr class="separator:gad639e19f23a2fcf293866343cb0a14b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97aee097a4dcc23d5b2cf292247a92d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga97aee097a4dcc23d5b2cf292247a92d4">XRFDC_ADC_FIFO_LTNCY_MB_OFFSET</a>&#160;&#160;&#160;0x284U</td></tr>
<tr class="memdesc:ga97aee097a4dcc23d5b2cf292247a92d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Latency measurement MSB Register.  <a href="group___overview.html#ga97aee097a4dcc23d5b2cf292247a92d4">More...</a><br/></td></tr>
<tr class="separator:ga97aee097a4dcc23d5b2cf292247a92d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e226a0a8cb536930a8755160afef0b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4e226a0a8cb536930a8755160afef0b3">XRFDC_DAC_DECODER_CTRL_OFFSET</a>&#160;&#160;&#160;0x180U</td></tr>
<tr class="memdesc:ga4e226a0a8cb536930a8755160afef0b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Unary Decoder/ Randomizer settings.  <a href="group___overview.html#ga4e226a0a8cb536930a8755160afef0b3">More...</a><br/></td></tr>
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<tr class="memitem:ga0cc20a9ffe3f8b77fbc5ccf52fcdece0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0cc20a9ffe3f8b77fbc5ccf52fcdece0">XRFDC_DAC_DECODER_CLK_OFFSET</a>&#160;&#160;&#160;0x184U</td></tr>
<tr class="memdesc:ga0cc20a9ffe3f8b77fbc5ccf52fcdece0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decoder Clock enable.  <a href="group___overview.html#ga0cc20a9ffe3f8b77fbc5ccf52fcdece0">More...</a><br/></td></tr>
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<tr class="memitem:ga678f9399a4c435bd853cd781e338d859"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga678f9399a4c435bd853cd781e338d859">XRFDC_MB_CONFIG_OFFSET</a>&#160;&#160;&#160;0x308U</td></tr>
<tr class="memdesc:ga678f9399a4c435bd853cd781e338d859"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiband Config status.  <a href="group___overview.html#ga678f9399a4c435bd853cd781e338d859">More...</a><br/></td></tr>
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<tr class="memitem:ga6bf5f2749b975c1438cf616ace8d9cf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6bf5f2749b975c1438cf616ace8d9cf5">XRFDC_ADC_SIG_DETECT_CTRL_OFFSET</a>&#160;&#160;&#160;0x114</td></tr>
<tr class="memdesc:ga6bf5f2749b975c1438cf616ace8d9cf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Signal Detector Control.  <a href="group___overview.html#ga6bf5f2749b975c1438cf616ace8d9cf5">More...</a><br/></td></tr>
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<tr class="memitem:ga981f11ef001e7db951a5a8689b35a834"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga981f11ef001e7db951a5a8689b35a834">XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET</a>&#160;&#160;&#160;0x118</td></tr>
<tr class="memdesc:ga981f11ef001e7db951a5a8689b35a834"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Signal Detector Threshold 0.  <a href="group___overview.html#ga981f11ef001e7db951a5a8689b35a834">More...</a><br/></td></tr>
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<tr class="memitem:ga2a71eba2a62cc09614ae99f28f978839"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2a71eba2a62cc09614ae99f28f978839">XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET</a>&#160;&#160;&#160;0x11C</td></tr>
<tr class="memdesc:ga2a71eba2a62cc09614ae99f28f978839"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Signal Detector Threshold 0 on Counter.  <a href="group___overview.html#ga2a71eba2a62cc09614ae99f28f978839">More...</a><br/></td></tr>
<tr class="separator:ga2a71eba2a62cc09614ae99f28f978839"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f41376ae3dfa8ecb3f7e941ec47b9b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6f41376ae3dfa8ecb3f7e941ec47b9b2">XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:ga6f41376ae3dfa8ecb3f7e941ec47b9b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Signal Detector Threshold 0 off Counter.  <a href="group___overview.html#ga6f41376ae3dfa8ecb3f7e941ec47b9b2">More...</a><br/></td></tr>
<tr class="separator:ga6f41376ae3dfa8ecb3f7e941ec47b9b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa67ab2c03336c3a227c7544970a1d542"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa67ab2c03336c3a227c7544970a1d542">XRFDC_ADC_SIG_DETECT_MAGN_OFFSET</a>&#160;&#160;&#160;0x130</td></tr>
<tr class="memdesc:gaa67ab2c03336c3a227c7544970a1d542"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Signal Detector Magintude.  <a href="group___overview.html#gaa67ab2c03336c3a227c7544970a1d542">More...</a><br/></td></tr>
<tr class="separator:gaa67ab2c03336c3a227c7544970a1d542"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga372af5c040222f82f0444ffce935cade"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga372af5c040222f82f0444ffce935cade">XRFDC_HSCOM_CLK_DSTR_OFFSET</a>&#160;&#160;&#160;0x088U</td></tr>
<tr class="memdesc:ga372af5c040222f82f0444ffce935cade"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Distribution Register.  <a href="group___overview.html#ga372af5c040222f82f0444ffce935cade">More...</a><br/></td></tr>
<tr class="separator:ga372af5c040222f82f0444ffce935cade"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae912b6d3a4ed2f38e98b532ac4400f54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae912b6d3a4ed2f38e98b532ac4400f54">XRFDC_HSCOM_CLK_DSTR_MASK</a>&#160;&#160;&#160;0xC788U</td></tr>
<tr class="memdesc:gae912b6d3a4ed2f38e98b532ac4400f54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Distribution Register.  <a href="group___overview.html#gae912b6d3a4ed2f38e98b532ac4400f54">More...</a><br/></td></tr>
<tr class="separator:gae912b6d3a4ed2f38e98b532ac4400f54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga832bf9156241ed1634d2c591d128bb02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga832bf9156241ed1634d2c591d128bb02">XRFDC_HSCOM_CLK_DSTR_MASK_ALT</a>&#160;&#160;&#160;0x1870U</td></tr>
<tr class="memdesc:ga832bf9156241ed1634d2c591d128bb02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Distribution Register for Intratile.  <a href="group___overview.html#ga832bf9156241ed1634d2c591d128bb02">More...</a><br/></td></tr>
<tr class="separator:ga832bf9156241ed1634d2c591d128bb02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8228c0e5440a1835d0ec58b4c9544615"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8228c0e5440a1835d0ec58b4c9544615">XRFDC_HSCOM_PWR_OFFSET</a>&#160;&#160;&#160;0x094</td></tr>
<tr class="memdesc:ga8228c0e5440a1835d0ec58b4c9544615"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control register during power-up sequence.  <a href="group___overview.html#ga8228c0e5440a1835d0ec58b4c9544615">More...</a><br/></td></tr>
<tr class="separator:ga8228c0e5440a1835d0ec58b4c9544615"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13a79e7c792cd12ec17b708411f078db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga13a79e7c792cd12ec17b708411f078db">XRFDC_HSCOM_CLK_DIV_OFFSET</a>&#160;&#160;&#160;0xB0</td></tr>
<tr class="memdesc:ga13a79e7c792cd12ec17b708411f078db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fabric clk out divider.  <a href="group___overview.html#ga13a79e7c792cd12ec17b708411f078db">More...</a><br/></td></tr>
<tr class="separator:ga13a79e7c792cd12ec17b708411f078db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf435fb23268bd664f1708e79aae3141a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf435fb23268bd664f1708e79aae3141a">XRFDC_HSCOM_PWR_STATE_OFFSET</a>&#160;&#160;&#160;0xB4</td></tr>
<tr class="memdesc:gaf435fb23268bd664f1708e79aae3141a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check powerup state.  <a href="group___overview.html#gaf435fb23268bd664f1708e79aae3141a">More...</a><br/></td></tr>
<tr class="separator:gaf435fb23268bd664f1708e79aae3141a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89f025f88acd17f1226901735df769d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga89f025f88acd17f1226901735df769d9">XRFDC_HSCOM_UPDT_DYN_OFFSET</a>&#160;&#160;&#160;0x0B8</td></tr>
<tr class="memdesc:ga89f025f88acd17f1226901735df769d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger the update dynamic event.  <a href="group___overview.html#ga89f025f88acd17f1226901735df769d9">More...</a><br/></td></tr>
<tr class="separator:ga89f025f88acd17f1226901735df769d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad7d23db0f88f4b4111f92f7448127b8b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad7d23db0f88f4b4111f92f7448127b8b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_HSCOM_EFUSE_2_OFFSET</b>&#160;&#160;&#160;0x144</td></tr>
<tr class="separator:gad7d23db0f88f4b4111f92f7448127b8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe01e9fab71fc942e2e76c8384186000"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafe01e9fab71fc942e2e76c8384186000">XRFDC_DAC_INVSINC_OFFSET</a>&#160;&#160;&#160;0x0C0U</td></tr>
<tr class="memdesc:gafe01e9fab71fc942e2e76c8384186000"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invsinc control.  <a href="group___overview.html#gafe01e9fab71fc942e2e76c8384186000">More...</a><br/></td></tr>
<tr class="separator:gafe01e9fab71fc942e2e76c8384186000"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga738d73a6d313704be82dc2908c289056"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga738d73a6d313704be82dc2908c289056">XRFDC_DAC_MB_CFG_OFFSET</a>&#160;&#160;&#160;0x0C4U</td></tr>
<tr class="memdesc:ga738d73a6d313704be82dc2908c289056"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiband config.  <a href="group___overview.html#ga738d73a6d313704be82dc2908c289056">More...</a><br/></td></tr>
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<tr class="memitem:gabbedc42054b2e403bc97dd9a8e10f0af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabbedc42054b2e403bc97dd9a8e10f0af"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRDIST</b>&#160;&#160;&#160;0x1CA0U</td></tr>
<tr class="separator:gabbedc42054b2e403bc97dd9a8e10f0af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e4e7dff0984af88860bfc355e72881f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2e4e7dff0984af88860bfc355e72881f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_T1</b>&#160;&#160;&#160;(0x24U &lt;&lt; 2U)</td></tr>
<tr class="separator:ga2e4e7dff0984af88860bfc355e72881f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae7e5aee4146aebb387aebae9d396031"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaae7e5aee4146aebb387aebae9d396031"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_PLL</b>&#160;&#160;&#160;(0x0CU &lt;&lt; 2U)</td></tr>
<tr class="separator:gaae7e5aee4146aebb387aebae9d396031"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac81ded91a794dd8965ef275483b8941c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac81ded91a794dd8965ef275483b8941c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_DIG</b>&#160;&#160;&#160;(0x2CU &lt;&lt; 2U)</td></tr>
<tr class="separator:gac81ded91a794dd8965ef275483b8941c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4104385da7134d4820af3100f4c6b765"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4104385da7134d4820af3100f4c6b765"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRDTC_T1</b>&#160;&#160;&#160;(0x27U &lt;&lt; 2U)</td></tr>
<tr class="separator:ga4104385da7134d4820af3100f4c6b765"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1430e0bb34a1806fb8c34f5c76c90224"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1430e0bb34a1806fb8c34f5c76c90224"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRDTC_PLL</b>&#160;&#160;&#160;(0x26U &lt;&lt; 2U)</td></tr>
<tr class="separator:ga1430e0bb34a1806fb8c34f5c76c90224"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e203ce5441814dd3c293da5dbb57b10"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e203ce5441814dd3c293da5dbb57b10"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRFLAG</b>&#160;&#160;&#160;(0x49U &lt;&lt; 2U)</td></tr>
<tr class="separator:ga3e203ce5441814dd3c293da5dbb57b10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadac4ab3893c66e3810de4203bb2280c3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadac4ab3893c66e3810de4203bb2280c3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_CLKSTAT</b>&#160;&#160;&#160;(0x24U &lt;&lt; 2U)</td></tr>
<tr class="separator:gadac4ab3893c66e3810de4203bb2280c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabac908132e8e9107615ef5af7ab006fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabac908132e8e9107615ef5af7ab006fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCOUNT_CTRL</b>&#160;&#160;&#160;0x004CU</td></tr>
<tr class="separator:gabac908132e8e9107615ef5af7ab006fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c0d73067cecde0e35b8f676a3d1ce20"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4c0d73067cecde0e35b8f676a3d1ce20"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCOUNT_VAL</b>&#160;&#160;&#160;0x0050U</td></tr>
<tr class="separator:ga4c0d73067cecde0e35b8f676a3d1ce20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca4743f0ae720c1cd65651dbcf7841cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca4743f0ae720c1cd65651dbcf7841cb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRFREQ_VAL</b>&#160;&#160;&#160;0x0054U</td></tr>
<tr class="separator:gaca4743f0ae720c1cd65651dbcf7841cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga224dabc4ad8a5292056e6514c2752da5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga224dabc4ad8a5292056e6514c2752da5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_FIFO_CTRL_ADC</b>&#160;&#160;&#160;0x0010U</td></tr>
<tr class="separator:ga224dabc4ad8a5292056e6514c2752da5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6f06605a3bcf5c6f1adf2dd19accbd4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad6f06605a3bcf5c6f1adf2dd19accbd4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_FIFO_CTRL_DAC</b>&#160;&#160;&#160;0x0014U</td></tr>
<tr class="separator:gad6f06605a3bcf5c6f1adf2dd19accbd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1bc967227099e4711c149bf97ae5722c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1bc967227099e4711c149bf97ae5722c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DELAY_CTRL</b>&#160;&#160;&#160;0x0028U</td></tr>
<tr class="separator:ga1bc967227099e4711c149bf97ae5722c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59d71de01e02defad9d0f233f4bd8387"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga59d71de01e02defad9d0f233f4bd8387"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_ADC_MARKER</b>&#160;&#160;&#160;0x0018U</td></tr>
<tr class="separator:ga59d71de01e02defad9d0f233f4bd8387"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab866681a93b6e790ea9d84dfac8ff5d8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab866681a93b6e790ea9d84dfac8ff5d8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_ADC_MARKER_CNT</b>&#160;&#160;&#160;0x0010U</td></tr>
<tr class="separator:gab866681a93b6e790ea9d84dfac8ff5d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga99f754fc63e8250c111c6fc612cf5511"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga99f754fc63e8250c111c6fc612cf5511"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DAC_MARKER_CTRL</b>&#160;&#160;&#160;0x0048U</td></tr>
<tr class="separator:ga99f754fc63e8250c111c6fc612cf5511"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga448bcf64aacf265e26b690734f6fd18c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga448bcf64aacf265e26b690734f6fd18c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DAC_MARKER_CNT</b>&#160;&#160;&#160;(0x92U &lt;&lt; 2U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DAC_MARKER_LOC</b>&#160;&#160;&#160;(0x93U &lt;&lt; 2U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DAC_FIFO_MARKER_CTRL</b>&#160;&#160;&#160;(0x94U &lt;&lt; 2U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DAC_FABRIC_OFFSET</b>&#160;&#160;&#160;0x0C</td></tr>
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<tr class="memitem:ga11e0f8900ba277a93fd6d4738d0b68ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga11e0f8900ba277a93fd6d4738d0b68ba">XRFDC_RESET_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga11e0f8900ba277a93fd6d4738d0b68ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tile reset register.  <a href="group___overview.html#ga11e0f8900ba277a93fd6d4738d0b68ba">More...</a><br/></td></tr>
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<tr class="memitem:ga5bdde5c28d587536e34f52557dc49c1a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5bdde5c28d587536e34f52557dc49c1a">XRFDC_RESTART_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga5bdde5c28d587536e34f52557dc49c1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tile restart register.  <a href="group___overview.html#ga5bdde5c28d587536e34f52557dc49c1a">More...</a><br/></td></tr>
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<tr class="memitem:ga357df0ca66868d9c3403472ecc0e32d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga357df0ca66868d9c3403472ecc0e32d8">XRFDC_RESTART_STATE_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:ga357df0ca66868d9c3403472ecc0e32d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tile restart state register.  <a href="group___overview.html#ga357df0ca66868d9c3403472ecc0e32d8">More...</a><br/></td></tr>
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<tr class="memitem:gab98c4ce2e63354a1c1e4cb014540cd54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab98c4ce2e63354a1c1e4cb014540cd54">XRFDC_CURRENT_STATE_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:gab98c4ce2e63354a1c1e4cb014540cd54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current state register.  <a href="group___overview.html#gab98c4ce2e63354a1c1e4cb014540cd54">More...</a><br/></td></tr>
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<tr class="memitem:gab59f83533097beeadc8c38f9b2d9b476"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab59f83533097beeadc8c38f9b2d9b476">XRFDC_CLOCK_DETECT_OFFSET</a>&#160;&#160;&#160;0x80U</td></tr>
<tr class="memdesc:gab59f83533097beeadc8c38f9b2d9b476"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock detect register.  <a href="group___overview.html#gab59f83533097beeadc8c38f9b2d9b476">More...</a><br/></td></tr>
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<tr class="memitem:gab8951c0ea0af304909c87b7b80b9023b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab8951c0ea0af304909c87b7b80b9023b">XRFDC_STATUS_OFFSET</a>&#160;&#160;&#160;0x228U</td></tr>
<tr class="memdesc:gab8951c0ea0af304909c87b7b80b9023b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common status register.  <a href="group___overview.html#gab8951c0ea0af304909c87b7b80b9023b">More...</a><br/></td></tr>
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<tr class="memitem:gac097c2bbfe5b553d2400bbf89de63b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac097c2bbfe5b553d2400bbf89de63b05">XRFDC_CAL_DIV_BYP_OFFSET</a>&#160;&#160;&#160;0x100U</td></tr>
<tr class="memdesc:gac097c2bbfe5b553d2400bbf89de63b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration divider bypass register.  <a href="group___overview.html#gac097c2bbfe5b553d2400bbf89de63b05">More...</a><br/></td></tr>
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<tr class="memitem:gabaa3a5ffa7b8ceb71a6a0a6368db1cc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabaa3a5ffa7b8ceb71a6a0a6368db1cc5">XRFDC_COMMON_INTR_STS</a>&#160;&#160;&#160;0x100U</td></tr>
<tr class="memdesc:gabaa3a5ffa7b8ceb71a6a0a6368db1cc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common Intr Status register.  <a href="group___overview.html#gabaa3a5ffa7b8ceb71a6a0a6368db1cc5">More...</a><br/></td></tr>
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<tr class="memitem:gabaa1d95b73e1c8d9c1709e0d8abc1f46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabaa1d95b73e1c8d9c1709e0d8abc1f46">XRFDC_COMMON_INTR_ENABLE</a>&#160;&#160;&#160;0x104U</td></tr>
<tr class="memdesc:gabaa1d95b73e1c8d9c1709e0d8abc1f46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common Intr enable register.  <a href="group___overview.html#gabaa1d95b73e1c8d9c1709e0d8abc1f46">More...</a><br/></td></tr>
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<tr class="memitem:ga6e7ebb889b6ad83a14ad8c76202c2a75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6e7ebb889b6ad83a14ad8c76202c2a75">XRFDC_INTR_STS</a>&#160;&#160;&#160;0x200U</td></tr>
<tr class="memdesc:ga6e7ebb889b6ad83a14ad8c76202c2a75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr status register.  <a href="group___overview.html#ga6e7ebb889b6ad83a14ad8c76202c2a75">More...</a><br/></td></tr>
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<tr class="memitem:ga1b75af0597b8e14a9d731bbbe4b33377"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1b75af0597b8e14a9d731bbbe4b33377">XRFDC_INTR_ENABLE</a>&#160;&#160;&#160;0x204U</td></tr>
<tr class="memdesc:ga1b75af0597b8e14a9d731bbbe4b33377"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr enable register.  <a href="group___overview.html#ga1b75af0597b8e14a9d731bbbe4b33377">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CONV_INTR_STS</b>(X)&#160;&#160;&#160;(0x208U + (X * 0x08U))</td></tr>
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<tr class="memitem:ga80eecee8b7319e88c29aa07061c6c661"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga80eecee8b7319e88c29aa07061c6c661"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CONV_INTR_EN</b>(X)&#160;&#160;&#160;(0x20CU + (X * 0x08U))</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CONV_CAL_STGS</b>(X)&#160;&#160;&#160;(0x234U + (X * 0x04U))</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CONV_DSA_STGS</b>(X)&#160;&#160;&#160;(0x244U + (X * 0x04U))</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CAL_GCB_COEFF0_FAB</b>(X)&#160;&#160;&#160;(0x280U + (X * 0x10U))</td></tr>
<tr class="separator:ga16569821dea5ff77cc62777f89194369"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38e6d1688bcb6ec94534bc1f7ab343ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga38e6d1688bcb6ec94534bc1f7ab343ec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CAL_GCB_COEFF1_FAB</b>(X)&#160;&#160;&#160;(0x284U + (X * 0x10U))</td></tr>
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<tr class="memitem:gafcbde085e361dd10e82172d6d899ba23"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafcbde085e361dd10e82172d6d899ba23"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CAL_GCB_COEFF2_FAB</b>(X)&#160;&#160;&#160;(0x288U + (X * 0x10U))</td></tr>
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<tr class="memitem:gac4796572cc3f91df2c60d32dc296451d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac4796572cc3f91df2c60d32dc296451d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_CAL_GCB_COEFF3_FAB</b>(X)&#160;&#160;&#160;(0x28CU + (X * 0x10U))</td></tr>
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<tr class="memitem:ga891cf1d15ecbe0f860e2497ffdbe8841"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga891cf1d15ecbe0f860e2497ffdbe8841">XRFDC_TDD_CTRL_SLICE_OFFSET</a>(X)&#160;&#160;&#160;(0x260 + (X * 0x04U))</td></tr>
<tr class="memdesc:ga891cf1d15ecbe0f860e2497ffdbe8841"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDD control registers.  <a href="group___overview.html#ga891cf1d15ecbe0f860e2497ffdbe8841">More...</a><br/></td></tr>
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<tr class="memitem:ga606e1e2542c9ccd2219eee93c120b696"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga606e1e2542c9ccd2219eee93c120b696">XRFDC_PLL_FREQ</a>&#160;&#160;&#160;0x300U</td></tr>
<tr class="memdesc:ga606e1e2542c9ccd2219eee93c120b696"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL output frequency (before divider) register.  <a href="group___overview.html#ga606e1e2542c9ccd2219eee93c120b696">More...</a><br/></td></tr>
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<tr class="memitem:ga1c560029b8d261b859e5b035497c733f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1c560029b8d261b859e5b035497c733f">XRFDC_PLL_FS</a>&#160;&#160;&#160;0x304U</td></tr>
<tr class="memdesc:ga1c560029b8d261b859e5b035497c733f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sampling rate register.  <a href="group___overview.html#ga1c560029b8d261b859e5b035497c733f">More...</a><br/></td></tr>
<tr class="separator:ga1c560029b8d261b859e5b035497c733f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b6a9682f7f0830110f82bc2e10f305d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6b6a9682f7f0830110f82bc2e10f305d">XRFDC_CAL_TMR_MULT_OFFSET</a>&#160;&#160;&#160;0x30CU</td></tr>
<tr class="memdesc:ga6b6a9682f7f0830110f82bc2e10f305d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration timer register.  <a href="group___overview.html#ga6b6a9682f7f0830110f82bc2e10f305d">More...</a><br/></td></tr>
<tr class="separator:ga6b6a9682f7f0830110f82bc2e10f305d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae222d8785778e4814c2883d0aa42219b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae222d8785778e4814c2883d0aa42219b">XRFDC_CAL_DLY_OFFSET</a>&#160;&#160;&#160;0x310U</td></tr>
<tr class="memdesc:gae222d8785778e4814c2883d0aa42219b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration delay register.  <a href="group___overview.html#gae222d8785778e4814c2883d0aa42219b">More...</a><br/></td></tr>
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<tr class="memitem:gaf9a26d52caa98a399dc42bc12f8b23f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf9a26d52caa98a399dc42bc12f8b23f1">XRFDC_CPL_TYPE_OFFSET</a>&#160;&#160;&#160;0x314U</td></tr>
<tr class="memdesc:gaf9a26d52caa98a399dc42bc12f8b23f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coupling type register.  <a href="group___overview.html#gaf9a26d52caa98a399dc42bc12f8b23f1">More...</a><br/></td></tr>
<tr class="separator:gaf9a26d52caa98a399dc42bc12f8b23f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga670e05de2e491e8d3662629895285bdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga670e05de2e491e8d3662629895285bdd">XRFDC_FIFO_ENABLE</a>&#160;&#160;&#160;0x230U</td></tr>
<tr class="memdesc:ga670e05de2e491e8d3662629895285bdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Enable and Disable.  <a href="group___overview.html#ga670e05de2e491e8d3662629895285bdd">More...</a><br/></td></tr>
<tr class="separator:ga670e05de2e491e8d3662629895285bdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e3a070158185916ebaa7501ac9d29fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6e3a070158185916ebaa7501ac9d29fd">XRFDC_PLL_SDM_CFG0</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga6e3a070158185916ebaa7501ac9d29fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Configuration bits for sdm.  <a href="group___overview.html#ga6e3a070158185916ebaa7501ac9d29fd">More...</a><br/></td></tr>
<tr class="separator:ga6e3a070158185916ebaa7501ac9d29fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga758834f94068939ad00179e1f03b7b3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga758834f94068939ad00179e1f03b7b3a">XRFDC_PLL_SDM_SEED0</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:ga758834f94068939ad00179e1f03b7b3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Bits for sdm LSB.  <a href="group___overview.html#ga758834f94068939ad00179e1f03b7b3a">More...</a><br/></td></tr>
<tr class="separator:ga758834f94068939ad00179e1f03b7b3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga405ed2792dc5d1e4fe5a3b7e8569ecc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga405ed2792dc5d1e4fe5a3b7e8569ecc1">XRFDC_PLL_SDM_SEED1</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga405ed2792dc5d1e4fe5a3b7e8569ecc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Bits for sdm MSB.  <a href="group___overview.html#ga405ed2792dc5d1e4fe5a3b7e8569ecc1">More...</a><br/></td></tr>
<tr class="separator:ga405ed2792dc5d1e4fe5a3b7e8569ecc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21e08740f4f2a45a4babe1a0a44eabeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga21e08740f4f2a45a4babe1a0a44eabeb">XRFDC_PLL_VREG</a>&#160;&#160;&#160;0x44U</td></tr>
<tr class="memdesc:ga21e08740f4f2a45a4babe1a0a44eabeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for voltage regulator.  <a href="group___overview.html#ga21e08740f4f2a45a4babe1a0a44eabeb">More...</a><br/></td></tr>
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<tr class="memitem:ga9b83cfd956fb25f99e122a772c22049f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9b83cfd956fb25f99e122a772c22049f">XRFDC_PLL_VCO0</a>&#160;&#160;&#160;0x54U</td></tr>
<tr class="memdesc:ga9b83cfd956fb25f99e122a772c22049f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for coltage controlled oscillator LSB.  <a href="group___overview.html#ga9b83cfd956fb25f99e122a772c22049f">More...</a><br/></td></tr>
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<tr class="memitem:gafe4103ee0e8477690117770e764b5ede"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafe4103ee0e8477690117770e764b5ede">XRFDC_PLL_VCO1</a>&#160;&#160;&#160;0x58U</td></tr>
<tr class="memdesc:gafe4103ee0e8477690117770e764b5ede"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for coltage controlled oscillator MSB.  <a href="group___overview.html#gafe4103ee0e8477690117770e764b5ede">More...</a><br/></td></tr>
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<tr class="memitem:gad4d26d656dea0fa3ac7ccbaa2e80b8cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad4d26d656dea0fa3ac7ccbaa2e80b8cf">XRFDC_PLL_CRS1</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:gad4d26d656dea0fa3ac7ccbaa2e80b8cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for coarse frequency control LSB.  <a href="group___overview.html#gad4d26d656dea0fa3ac7ccbaa2e80b8cf">More...</a><br/></td></tr>
<tr class="separator:gad4d26d656dea0fa3ac7ccbaa2e80b8cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64fd35006a56aa7c109dcfcd0ebc7f40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga64fd35006a56aa7c109dcfcd0ebc7f40">XRFDC_PLL_CRS2</a>&#160;&#160;&#160;0x2CU</td></tr>
<tr class="memdesc:ga64fd35006a56aa7c109dcfcd0ebc7f40"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for coarse frequency control MSB.  <a href="group___overview.html#ga64fd35006a56aa7c109dcfcd0ebc7f40">More...</a><br/></td></tr>
<tr class="separator:ga64fd35006a56aa7c109dcfcd0ebc7f40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac73689ba185afcdcf7811674fd436ed5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac73689ba185afcdcf7811674fd436ed5">XRFDC_PLL_DIVIDER0</a>&#160;&#160;&#160;0x30U</td></tr>
<tr class="memdesc:gac73689ba185afcdcf7811674fd436ed5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Output Divider LSB register.  <a href="group___overview.html#gac73689ba185afcdcf7811674fd436ed5">More...</a><br/></td></tr>
<tr class="separator:gac73689ba185afcdcf7811674fd436ed5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2ba73b38f13731eb9ba654b4a1d58a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2ba73b38f13731eb9ba654b4a1d58a8f">XRFDC_PLL_DIVIDER1</a>&#160;&#160;&#160;0x34U</td></tr>
<tr class="memdesc:ga2ba73b38f13731eb9ba654b4a1d58a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Output Divider MSB register.  <a href="group___overview.html#ga2ba73b38f13731eb9ba654b4a1d58a8f">More...</a><br/></td></tr>
<tr class="separator:ga2ba73b38f13731eb9ba654b4a1d58a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb5c753b89ae5096036a064c7be809b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacb5c753b89ae5096036a064c7be809b0">XRFDC_PLL_SPARE0</a>&#160;&#160;&#160;0x38U</td></tr>
<tr class="memdesc:gacb5c753b89ae5096036a064c7be809b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL spare inputs LSB.  <a href="group___overview.html#gacb5c753b89ae5096036a064c7be809b0">More...</a><br/></td></tr>
<tr class="separator:gacb5c753b89ae5096036a064c7be809b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae377d265350f9ab5046a2e932ed904b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae377d265350f9ab5046a2e932ed904b3">XRFDC_PLL_SPARE1</a>&#160;&#160;&#160;0x3CU</td></tr>
<tr class="memdesc:gae377d265350f9ab5046a2e932ed904b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL spare inputs MSB.  <a href="group___overview.html#gae377d265350f9ab5046a2e932ed904b3">More...</a><br/></td></tr>
<tr class="separator:gae377d265350f9ab5046a2e932ed904b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaddc1e251944bdd70439c00ea2b91a4a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaddc1e251944bdd70439c00ea2b91a4a1">XRFDC_PLL_REFDIV</a>&#160;&#160;&#160;0x40U</td></tr>
<tr class="memdesc:gaddc1e251944bdd70439c00ea2b91a4a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Reference Divider register.  <a href="group___overview.html#gaddc1e251944bdd70439c00ea2b91a4a1">More...</a><br/></td></tr>
<tr class="separator:gaddc1e251944bdd70439c00ea2b91a4a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21e08740f4f2a45a4babe1a0a44eabeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga21e08740f4f2a45a4babe1a0a44eabeb">XRFDC_PLL_VREG</a>&#160;&#160;&#160;0x44U</td></tr>
<tr class="memdesc:ga21e08740f4f2a45a4babe1a0a44eabeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for voltage regulator.  <a href="group___overview.html#ga21e08740f4f2a45a4babe1a0a44eabeb">More...</a><br/></td></tr>
<tr class="separator:ga21e08740f4f2a45a4babe1a0a44eabeb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f25bb874f2dabf8cc76e163b0e56fa2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2f25bb874f2dabf8cc76e163b0e56fa2">XRFDC_PLL_CHARGEPUMP</a>&#160;&#160;&#160;0x48U</td></tr>
<tr class="memdesc:ga2f25bb874f2dabf8cc76e163b0e56fa2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for charge pumps.  <a href="group___overview.html#ga2f25bb874f2dabf8cc76e163b0e56fa2">More...</a><br/></td></tr>
<tr class="separator:ga2f25bb874f2dabf8cc76e163b0e56fa2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga999aad3b01648188b4868dc8c7ac402f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga999aad3b01648188b4868dc8c7ac402f">XRFDC_PLL_LPF0</a>&#160;&#160;&#160;0x4CU</td></tr>
<tr class="memdesc:ga999aad3b01648188b4868dc8c7ac402f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for loop filters LSB.  <a href="group___overview.html#ga999aad3b01648188b4868dc8c7ac402f">More...</a><br/></td></tr>
<tr class="separator:ga999aad3b01648188b4868dc8c7ac402f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d6e2a5cf549565eba10c8025e301c03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3d6e2a5cf549565eba10c8025e301c03">XRFDC_PLL_LPF1</a>&#160;&#160;&#160;0x50U</td></tr>
<tr class="memdesc:ga3d6e2a5cf549565eba10c8025e301c03"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL bits for loop filters MSB.  <a href="group___overview.html#ga3d6e2a5cf549565eba10c8025e301c03">More...</a><br/></td></tr>
<tr class="separator:ga3d6e2a5cf549565eba10c8025e301c03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc0c3fc190c2d7a0466fcd73ff497db8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacc0c3fc190c2d7a0466fcd73ff497db8">XRFDC_PLL_FPDIV</a>&#160;&#160;&#160;0x5CU</td></tr>
<tr class="memdesc:gacc0c3fc190c2d7a0466fcd73ff497db8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Feedback Divider register.  <a href="group___overview.html#gacc0c3fc190c2d7a0466fcd73ff497db8">More...</a><br/></td></tr>
<tr class="separator:gacc0c3fc190c2d7a0466fcd73ff497db8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga42436dcd000344859cc2b3c828ee0ebc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga42436dcd000344859cc2b3c828ee0ebc">XRFDC_CLK_NETWORK_CTRL0</a>&#160;&#160;&#160;0x8CU</td></tr>
<tr class="memdesc:ga42436dcd000344859cc2b3c828ee0ebc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock network control and trim register.  <a href="group___overview.html#ga42436dcd000344859cc2b3c828ee0ebc">More...</a><br/></td></tr>
<tr class="separator:ga42436dcd000344859cc2b3c828ee0ebc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3f8b6206a330b53ad8f5c7e626c357e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa3f8b6206a330b53ad8f5c7e626c357e">XRFDC_CLK_NETWORK_CTRL1</a>&#160;&#160;&#160;0x90U</td></tr>
<tr class="memdesc:gaa3f8b6206a330b53ad8f5c7e626c357e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi-tile sync and clock source control register.  <a href="group___overview.html#gaa3f8b6206a330b53ad8f5c7e626c357e">More...</a><br/></td></tr>
<tr class="separator:gaa3f8b6206a330b53ad8f5c7e626c357e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga245743becc464428c00a9083f1ce7994"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga245743becc464428c00a9083f1ce7994">XRFDC_HSCOM_NETWORK_CTRL1_MASK</a>&#160;&#160;&#160;0x02FU</td></tr>
<tr class="memdesc:ga245743becc464428c00a9083f1ce7994"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Network Register Mask for IntraTile.  <a href="group___overview.html#ga245743becc464428c00a9083f1ce7994">More...</a><br/></td></tr>
<tr class="separator:ga245743becc464428c00a9083f1ce7994"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29d68c85ca57823080a838bfb9868708"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga29d68c85ca57823080a838bfb9868708">XRFDC_PLL_REFDIV_MASK</a>&#160;&#160;&#160;0x0E0U</td></tr>
<tr class="memdesc:ga29d68c85ca57823080a838bfb9868708"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Reference Divider Register Mask for IntraTile.  <a href="group___overview.html#ga29d68c85ca57823080a838bfb9868708">More...</a><br/></td></tr>
<tr class="separator:ga29d68c85ca57823080a838bfb9868708"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacecadaaeb86da41f9c0a3257ace61a9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacecadaaeb86da41f9c0a3257ace61a9f">XRFDC_PLL_DIVIDER0_ALT_MASK</a>&#160;&#160;&#160;0xC00U</td></tr>
<tr class="memdesc:gacecadaaeb86da41f9c0a3257ace61a9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Output Divider Register Mask for IntraTile.  <a href="group___overview.html#gacecadaaeb86da41f9c0a3257ace61a9f">More...</a><br/></td></tr>
<tr class="separator:gacecadaaeb86da41f9c0a3257ace61a9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00cdd4494f0eab9160f9b2c062309680"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga00cdd4494f0eab9160f9b2c062309680">XRFDC_PLL_DIVIDER0_BYPPLL_MASK</a>&#160;&#160;&#160;0x800U</td></tr>
<tr class="memdesc:ga00cdd4494f0eab9160f9b2c062309680"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Output Divider Register Mask for IntraTile.  <a href="group___overview.html#ga00cdd4494f0eab9160f9b2c062309680">More...</a><br/></td></tr>
<tr class="separator:ga00cdd4494f0eab9160f9b2c062309680"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab9d9eb05a7cdad573b83898a72b4d23d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab9d9eb05a7cdad573b83898a72b4d23d">XRFDC_PLL_DIVIDER0_BYPDIV_MASK</a>&#160;&#160;&#160;0x400U</td></tr>
<tr class="memdesc:gab9d9eb05a7cdad573b83898a72b4d23d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Output Divider Register Mask for IntraTile.  <a href="group___overview.html#gab9d9eb05a7cdad573b83898a72b4d23d">More...</a><br/></td></tr>
<tr class="separator:gab9d9eb05a7cdad573b83898a72b4d23d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga564dc93ac3c36b182492e27ebae8b179"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga564dc93ac3c36b182492e27ebae8b179">XRFDC_CAL_OCB1_OFFSET_COEFF0</a>&#160;&#160;&#160;0x200</td></tr>
<tr class="memdesc:ga564dc93ac3c36b182492e27ebae8b179"><td class="mdescLeft">&#160;</td><td class="mdescRight">Foreground offset correction block.  <a href="group___overview.html#ga564dc93ac3c36b182492e27ebae8b179">More...</a><br/></td></tr>
<tr class="separator:ga564dc93ac3c36b182492e27ebae8b179"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa90b4c54425164dae19d4c1325bcd191"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa90b4c54425164dae19d4c1325bcd191">XRFDC_CAL_OCB1_OFFSET_COEFF1</a>&#160;&#160;&#160;0x208</td></tr>
<tr class="memdesc:gaa90b4c54425164dae19d4c1325bcd191"><td class="mdescLeft">&#160;</td><td class="mdescRight">Foreground offset correction block.  <a href="group___overview.html#gaa90b4c54425164dae19d4c1325bcd191">More...</a><br/></td></tr>
<tr class="separator:gaa90b4c54425164dae19d4c1325bcd191"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81a3cca638310bac179ed16469c7555d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga81a3cca638310bac179ed16469c7555d">XRFDC_CAL_OCB1_OFFSET_COEFF2</a>&#160;&#160;&#160;0x210</td></tr>
<tr class="memdesc:ga81a3cca638310bac179ed16469c7555d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Foreground offset correction block.  <a href="group___overview.html#ga81a3cca638310bac179ed16469c7555d">More...</a><br/></td></tr>
<tr class="separator:ga81a3cca638310bac179ed16469c7555d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d957c2eb92fcb87d3d71c0f8a34d116"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7d957c2eb92fcb87d3d71c0f8a34d116">XRFDC_CAL_OCB1_OFFSET_COEFF3</a>&#160;&#160;&#160;0x218</td></tr>
<tr class="memdesc:ga7d957c2eb92fcb87d3d71c0f8a34d116"><td class="mdescLeft">&#160;</td><td class="mdescRight">Foreground offset correction block.  <a href="group___overview.html#ga7d957c2eb92fcb87d3d71c0f8a34d116">More...</a><br/></td></tr>
<tr class="separator:ga7d957c2eb92fcb87d3d71c0f8a34d116"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab152252bffe268a3af58ac307bf2ce9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab152252bffe268a3af58ac307bf2ce9d">XRFDC_CAL_OCB2_OFFSET_COEFF0</a>&#160;&#160;&#160;0x204</td></tr>
<tr class="memdesc:gab152252bffe268a3af58ac307bf2ce9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Background offset correction block.  <a href="group___overview.html#gab152252bffe268a3af58ac307bf2ce9d">More...</a><br/></td></tr>
<tr class="separator:gab152252bffe268a3af58ac307bf2ce9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d9a5220dd4b5c5d1fba397f5b2a3126"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6d9a5220dd4b5c5d1fba397f5b2a3126">XRFDC_CAL_OCB2_OFFSET_COEFF1</a>&#160;&#160;&#160;0x20C</td></tr>
<tr class="memdesc:ga6d9a5220dd4b5c5d1fba397f5b2a3126"><td class="mdescLeft">&#160;</td><td class="mdescRight">Background offset correction block.  <a href="group___overview.html#ga6d9a5220dd4b5c5d1fba397f5b2a3126">More...</a><br/></td></tr>
<tr class="separator:ga6d9a5220dd4b5c5d1fba397f5b2a3126"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac041352f6b5fcffbc7971d3ad879b529"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac041352f6b5fcffbc7971d3ad879b529">XRFDC_CAL_OCB2_OFFSET_COEFF2</a>&#160;&#160;&#160;0x214</td></tr>
<tr class="memdesc:gac041352f6b5fcffbc7971d3ad879b529"><td class="mdescLeft">&#160;</td><td class="mdescRight">Background offset correction block.  <a href="group___overview.html#gac041352f6b5fcffbc7971d3ad879b529">More...</a><br/></td></tr>
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<tr class="memitem:ga9c97e79012fd89d3d8aa968f919c9b6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9c97e79012fd89d3d8aa968f919c9b6d">XRFDC_HSCOM_FIFO_START_OFFSET</a>&#160;&#160;&#160;0x0C0U</td></tr>
<tr class="memdesc:ga9c97e79012fd89d3d8aa968f919c9b6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Start register tommon along tile.  <a href="group___overview.html#ga9c97e79012fd89d3d8aa968f919c9b6d">More...</a><br/></td></tr>
<tr class="separator:ga9c97e79012fd89d3d8aa968f919c9b6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22227fe716cf6a4e290fced3e8010ec5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga22227fe716cf6a4e290fced3e8010ec5">XRFDC_HSCOM_FIFO_START_OBS_OFFSET</a>&#160;&#160;&#160;0x0BCU</td></tr>
<tr class="memdesc:ga22227fe716cf6a4e290fced3e8010ec5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Obs Start register common along tile.  <a href="group___overview.html#ga22227fe716cf6a4e290fced3e8010ec5">More...</a><br/></td></tr>
<tr class="separator:ga22227fe716cf6a4e290fced3e8010ec5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26e0c1b24b6ac2958b9c730675d91b5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga26e0c1b24b6ac2958b9c730675d91b5c">XRFDC_HSCOM_FIFO_START_TDD_OFFSET</a>(X)</td></tr>
<tr class="memdesc:ga26e0c1b24b6ac2958b9c730675d91b5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO Start (or OBS) register common along tile TDD Selected.  <a href="group___overview.html#ga26e0c1b24b6ac2958b9c730675d91b5c">More...</a><br/></td></tr>
<tr class="separator:ga26e0c1b24b6ac2958b9c730675d91b5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IP Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets from the base address of the IP. </p>
</div></td></tr>
<tr class="memitem:gabe23fae7ec9e16eeecb219861b60ac8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabe23fae7ec9e16eeecb219861b60ac8c">XRFDC_TILES_ENABLED_OFFSET</a>&#160;&#160;&#160;0x00A0U</td></tr>
<tr class="memdesc:gabe23fae7ec9e16eeecb219861b60ac8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The tiles enabled in the design.  <a href="group___overview.html#gabe23fae7ec9e16eeecb219861b60ac8c">More...</a><br/></td></tr>
<tr class="separator:gabe23fae7ec9e16eeecb219861b60ac8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a1b149f4b98223e183ae98e42d427dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a1b149f4b98223e183ae98e42d427dc">XRFDC_ADC_PATHS_ENABLED_OFFSET</a>&#160;&#160;&#160;0x00A4U</td></tr>
<tr class="memdesc:ga9a1b149f4b98223e183ae98e42d427dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">The ADC analogue/digital paths enabled in the design.  <a href="group___overview.html#ga9a1b149f4b98223e183ae98e42d427dc">More...</a><br/></td></tr>
<tr class="separator:ga9a1b149f4b98223e183ae98e42d427dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad76811c432a98a7c1b44ef7a4fc7e73d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad76811c432a98a7c1b44ef7a4fc7e73d">XRFDC_DAC_PATHS_ENABLED_OFFSET</a>&#160;&#160;&#160;0x00A8U</td></tr>
<tr class="memdesc:gad76811c432a98a7c1b44ef7a4fc7e73d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The DAC analogue/digital paths enabled in the design.  <a href="group___overview.html#gad76811c432a98a7c1b44ef7a4fc7e73d">More...</a><br/></td></tr>
<tr class="separator:gad76811c432a98a7c1b44ef7a4fc7e73d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26d2cbf4c02004cf6b8cf75594ac08b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga26d2cbf4c02004cf6b8cf75594ac08b7">XRFDC_PATH_ENABLED_TILE_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:ga26d2cbf4c02004cf6b8cf75594ac08b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">A shift to get to the correct tile for the path.  <a href="group___overview.html#ga26d2cbf4c02004cf6b8cf75594ac08b7">More...</a><br/></td></tr>
<tr class="separator:ga26d2cbf4c02004cf6b8cf75594ac08b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Tile State - Tile state register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for the current tile State. </p>
</div></td></tr>
<tr class="memitem:gae06126d8c431de4724f3e8c731ae6a54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae06126d8c431de4724f3e8c731ae6a54">XRFDC_CURRENT_STATE_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:gae06126d8c431de4724f3e8c731ae6a54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current tile state mask.  <a href="group___overview.html#gae06126d8c431de4724f3e8c731ae6a54">More...</a><br/></td></tr>
<tr class="separator:gae06126d8c431de4724f3e8c731ae6a54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Calibration Mode - Calibration mode registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for calibration modes for ADC. </p>
</div></td></tr>
<tr class="memitem:ga5ef87d211872ac609ee8d36c9bd9c057"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5ef87d211872ac609ee8d36c9bd9c057">XRFDC_CAL_MODES_MASK</a>&#160;&#160;&#160;0x0003U</td></tr>
<tr class="memdesc:ga5ef87d211872ac609ee8d36c9bd9c057"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration modes for Gen 3 mask.  <a href="group___overview.html#ga5ef87d211872ac609ee8d36c9bd9c057">More...</a><br/></td></tr>
<tr class="separator:ga5ef87d211872ac609ee8d36c9bd9c057"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Calibration Coefficients - Calibration coefficients and disable registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for calibration coefficients for ADC. </p>
</div></td></tr>
<tr class="memitem:ga947e6e7ff58d6762ac9f9b201929506a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga947e6e7ff58d6762ac9f9b201929506a">XRFDC_CAL_OCB_MASK</a>&#160;&#160;&#160;0xFFFFU</td></tr>
<tr class="memdesc:ga947e6e7ff58d6762ac9f9b201929506a"><td class="mdescLeft">&#160;</td><td class="mdescRight">offsets coeff mask  <a href="group___overview.html#ga947e6e7ff58d6762ac9f9b201929506a">More...</a><br/></td></tr>
<tr class="separator:ga947e6e7ff58d6762ac9f9b201929506a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59144c652e31fa6df85e3c978bc95c51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga59144c652e31fa6df85e3c978bc95c51">XRFDC_CAL_GCB_MASK</a>&#160;&#160;&#160;0x0FFFU</td></tr>
<tr class="memdesc:ga59144c652e31fa6df85e3c978bc95c51"><td class="mdescLeft">&#160;</td><td class="mdescRight">gain coeff mask  <a href="group___overview.html#ga59144c652e31fa6df85e3c978bc95c51">More...</a><br/></td></tr>
<tr class="separator:ga59144c652e31fa6df85e3c978bc95c51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b6721bd0d644668f0be51883f76a5f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1b6721bd0d644668f0be51883f76a5f1">XRFDC_CAL_GCB_FAB_MASK</a>&#160;&#160;&#160;0xFFF0U</td></tr>
<tr class="memdesc:ga1b6721bd0d644668f0be51883f76a5f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">gain coeff mask for IP Gen 2 or below  <a href="group___overview.html#ga1b6721bd0d644668f0be51883f76a5f1">More...</a><br/></td></tr>
<tr class="separator:ga1b6721bd0d644668f0be51883f76a5f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61af9d4e9550a321ee5895a5714ceb17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga61af9d4e9550a321ee5895a5714ceb17">XRFDC_CAL_TSCB_MASK</a>&#160;&#160;&#160;0x01FFU</td></tr>
<tr class="memdesc:ga61af9d4e9550a321ee5895a5714ceb17"><td class="mdescLeft">&#160;</td><td class="mdescRight">time skew coeff mask  <a href="group___overview.html#ga61af9d4e9550a321ee5895a5714ceb17">More...</a><br/></td></tr>
<tr class="separator:ga61af9d4e9550a321ee5895a5714ceb17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf54d7742818b98b043a3e61b763673d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf54d7742818b98b043a3e61b763673d5">XRFDC_CAL_GCB_FLSH_MASK</a>&#160;&#160;&#160;0x1000U</td></tr>
<tr class="memdesc:gaf54d7742818b98b043a3e61b763673d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCB accumulator flush mask.  <a href="group___overview.html#gaf54d7742818b98b043a3e61b763673d5">More...</a><br/></td></tr>
<tr class="separator:gaf54d7742818b98b043a3e61b763673d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade4ee2db05c71ebb5a100bf23342cca2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gade4ee2db05c71ebb5a100bf23342cca2">XRFDC_CAL_GCB_ACEN_MASK</a>&#160;&#160;&#160;0x0800U</td></tr>
<tr class="memdesc:gade4ee2db05c71ebb5a100bf23342cca2"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCB accumulator enable mask.  <a href="group___overview.html#gade4ee2db05c71ebb5a100bf23342cca2">More...</a><br/></td></tr>
<tr class="separator:gade4ee2db05c71ebb5a100bf23342cca2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac609a08b870473222480eaf9261f6a2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac609a08b870473222480eaf9261f6a2f">XRFDC_CAL_GCB_ENFL_MASK</a>&#160;&#160;&#160;0x1800U</td></tr>
<tr class="memdesc:gac609a08b870473222480eaf9261f6a2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCB accumulator enable mask.  <a href="group___overview.html#gac609a08b870473222480eaf9261f6a2f">More...</a><br/></td></tr>
<tr class="separator:gac609a08b870473222480eaf9261f6a2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf019b0fcb5b82865bf6dc8c0d5edde3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf019b0fcb5b82865bf6dc8c0d5edde3b">XRFDC_CAL_OCB_EN_MASK</a>&#160;&#160;&#160;0x0001U</td></tr>
<tr class="memdesc:gaf019b0fcb5b82865bf6dc8c0d5edde3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">offsets coeff override enable mask  <a href="group___overview.html#gaf019b0fcb5b82865bf6dc8c0d5edde3b">More...</a><br/></td></tr>
<tr class="separator:gaf019b0fcb5b82865bf6dc8c0d5edde3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35dcee39b35382ba955c6ce4103d106c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga35dcee39b35382ba955c6ce4103d106c">XRFDC_CAL_GCB_EN_MASK</a>&#160;&#160;&#160;0x2000U</td></tr>
<tr class="memdesc:ga35dcee39b35382ba955c6ce4103d106c"><td class="mdescLeft">&#160;</td><td class="mdescRight">gain coeff override enable mask  <a href="group___overview.html#ga35dcee39b35382ba955c6ce4103d106c">More...</a><br/></td></tr>
<tr class="separator:ga35dcee39b35382ba955c6ce4103d106c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6eb5f3832024803b92d81a2a0054faaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6eb5f3832024803b92d81a2a0054faaf">XRFDC_CAL_TSCB_EN_MASK</a>&#160;&#160;&#160;0x8000U</td></tr>
<tr class="memdesc:ga6eb5f3832024803b92d81a2a0054faaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">time skew coeff override enable mask  <a href="group___overview.html#ga6eb5f3832024803b92d81a2a0054faaf">More...</a><br/></td></tr>
<tr class="separator:ga6eb5f3832024803b92d81a2a0054faaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8aa3d87470afd8668af9388e285bbf77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8aa3d87470afd8668af9388e285bbf77">XRFDC_CAL_OCB_EN_SHIFT</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:ga8aa3d87470afd8668af9388e285bbf77"><td class="mdescLeft">&#160;</td><td class="mdescRight">offsets coeff shift  <a href="group___overview.html#ga8aa3d87470afd8668af9388e285bbf77">More...</a><br/></td></tr>
<tr class="separator:ga8aa3d87470afd8668af9388e285bbf77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23e4dd8c936a2f3b0a72ef68f7cd92d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga23e4dd8c936a2f3b0a72ef68f7cd92d8">XRFDC_CAL_GCB_EN_SHIFT</a>&#160;&#160;&#160;13U</td></tr>
<tr class="memdesc:ga23e4dd8c936a2f3b0a72ef68f7cd92d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">gain coeff shift  <a href="group___overview.html#ga23e4dd8c936a2f3b0a72ef68f7cd92d8">More...</a><br/></td></tr>
<tr class="separator:ga23e4dd8c936a2f3b0a72ef68f7cd92d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03522a4f24e3ea6bd723afcbf1f46605"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03522a4f24e3ea6bd723afcbf1f46605">XRFDC_CAL_TSCB_EN_SHIFT</a>&#160;&#160;&#160;15U</td></tr>
<tr class="memdesc:ga03522a4f24e3ea6bd723afcbf1f46605"><td class="mdescLeft">&#160;</td><td class="mdescRight">time skew coeff shift  <a href="group___overview.html#ga03522a4f24e3ea6bd723afcbf1f46605">More...</a><br/></td></tr>
<tr class="separator:ga03522a4f24e3ea6bd723afcbf1f46605"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4acaaea34698108b1c3301d870413ad5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4acaaea34698108b1c3301d870413ad5">XRFDC_CAL_GCB_FLSH_SHIFT</a>&#160;&#160;&#160;12U</td></tr>
<tr class="memdesc:ga4acaaea34698108b1c3301d870413ad5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCB accumulator flush shift.  <a href="group___overview.html#ga4acaaea34698108b1c3301d870413ad5">More...</a><br/></td></tr>
<tr class="separator:ga4acaaea34698108b1c3301d870413ad5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7e7ca16d31fce9f2b00ebaa732f9cc6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf7e7ca16d31fce9f2b00ebaa732f9cc6">XRFDC_CAL_GCB_ACEN_SHIFT</a>&#160;&#160;&#160;11U</td></tr>
<tr class="memdesc:gaf7e7ca16d31fce9f2b00ebaa732f9cc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">GCB accumulator enable shift.  <a href="group___overview.html#gaf7e7ca16d31fce9f2b00ebaa732f9cc6">More...</a><br/></td></tr>
<tr class="separator:gaf7e7ca16d31fce9f2b00ebaa732f9cc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41c229173512aac7302670186238bb20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga41c229173512aac7302670186238bb20">XRFDC_CAL_TSCB_TUNE_MASK</a>&#160;&#160;&#160;0x0FF0U</td></tr>
<tr class="memdesc:ga41c229173512aac7302670186238bb20"><td class="mdescLeft">&#160;</td><td class="mdescRight">time skew tuning mask  <a href="group___overview.html#ga41c229173512aac7302670186238bb20">More...</a><br/></td></tr>
<tr class="separator:ga41c229173512aac7302670186238bb20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2708c0ce505381a49735607d2d2be9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad2708c0ce505381a49735607d2d2be9a">XRFDC_CAL_SLICE_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:gad2708c0ce505381a49735607d2d2be9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient shift for HSADCs.  <a href="group___overview.html#gad2708c0ce505381a49735607d2d2be9a">More...</a><br/></td></tr>
<tr class="separator:gad2708c0ce505381a49735607d2d2be9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a51e0cf53554c64f747f03a151bc4f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7a51e0cf53554c64f747f03a151bc4f3">XRFDC_CAL_FREEZE_CAL_MASK</a>&#160;&#160;&#160;0x1U</td></tr>
<tr class="memdesc:ga7a51e0cf53554c64f747f03a151bc4f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze enable mask.  <a href="group___overview.html#ga7a51e0cf53554c64f747f03a151bc4f3">More...</a><br/></td></tr>
<tr class="separator:ga7a51e0cf53554c64f747f03a151bc4f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d081c2b53eb6cdcfc86228f5b7496d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6d081c2b53eb6cdcfc86228f5b7496d9">XRFDC_CAL_FREEZE_STS_MASK</a>&#160;&#160;&#160;0x2U</td></tr>
<tr class="memdesc:ga6d081c2b53eb6cdcfc86228f5b7496d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze status mask.  <a href="group___overview.html#ga6d081c2b53eb6cdcfc86228f5b7496d9">More...</a><br/></td></tr>
<tr class="separator:ga6d081c2b53eb6cdcfc86228f5b7496d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d8ce5ffa7b364cd747a15caf535f7fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5d8ce5ffa7b364cd747a15caf535f7fd">XRFDC_CAL_FREEZE_PIN_MASK</a>&#160;&#160;&#160;0x4U</td></tr>
<tr class="memdesc:ga5d8ce5ffa7b364cd747a15caf535f7fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze pin disable mask.  <a href="group___overview.html#ga5d8ce5ffa7b364cd747a15caf535f7fd">More...</a><br/></td></tr>
<tr class="separator:ga5d8ce5ffa7b364cd747a15caf535f7fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab534ded200ce730fc9c9a4b5a07a974f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab534ded200ce730fc9c9a4b5a07a974f">XRFDC_CAL_FREEZE_CAL_SHIFT</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:gab534ded200ce730fc9c9a4b5a07a974f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze enable shift.  <a href="group___overview.html#gab534ded200ce730fc9c9a4b5a07a974f">More...</a><br/></td></tr>
<tr class="separator:gab534ded200ce730fc9c9a4b5a07a974f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadffb372abd94ddc5e7525d138437599a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadffb372abd94ddc5e7525d138437599a">XRFDC_CAL_FREEZE_STS_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:gadffb372abd94ddc5e7525d138437599a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze status shift.  <a href="group___overview.html#gadffb372abd94ddc5e7525d138437599a">More...</a><br/></td></tr>
<tr class="separator:gadffb372abd94ddc5e7525d138437599a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad617e05fdc5e2221d3633b18102d89e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad617e05fdc5e2221d3633b18102d89e1">XRFDC_CAL_FREEZE_PIN_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gad617e05fdc5e2221d3633b18102d89e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calibration freeze pin disable shift.  <a href="group___overview.html#gad617e05fdc5e2221d3633b18102d89e1">More...</a><br/></td></tr>
<tr class="separator:gad617e05fdc5e2221d3633b18102d89e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Enable - FIFO enable and disable register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for FIFO enable and disable for ADC and DAC. </p>
</div></td></tr>
<tr class="memitem:ga45c84a78b951cf790e724a495dfa3fa7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga45c84a78b951cf790e724a495dfa3fa7">XRFDC_FIFO_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga45c84a78b951cf790e724a495dfa3fa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO enable/disable mask.  <a href="group___overview.html#ga45c84a78b951cf790e724a495dfa3fa7">More...</a><br/></td></tr>
<tr class="separator:ga45c84a78b951cf790e724a495dfa3fa7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8903718edca26825af20cbbc832324ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8903718edca26825af20cbbc832324ac">XRFDC_FIFO_EN_OBS_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga8903718edca26825af20cbbc832324ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO OBS enable/disable mask.  <a href="group___overview.html#ga8903718edca26825af20cbbc832324ac">More...</a><br/></td></tr>
<tr class="separator:ga8903718edca26825af20cbbc832324ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23eabb61bc5561b297ea6c7309587411"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga23eabb61bc5561b297ea6c7309587411">XRFDC_FIFO_EN_OBS_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga23eabb61bc5561b297ea6c7309587411"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO OBS enable/disable shift.  <a href="group___overview.html#ga23eabb61bc5561b297ea6c7309587411">More...</a><br/></td></tr>
<tr class="separator:ga23eabb61bc5561b297ea6c7309587411"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1df7d98bd6097267167a028bf2f1c254"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1df7d98bd6097267167a028bf2f1c254">XRFDC_RESTART_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga1df7d98bd6097267167a028bf2f1c254"><td class="mdescLeft">&#160;</td><td class="mdescRight">Restart bit mask.  <a href="group___overview.html#ga1df7d98bd6097267167a028bf2f1c254">More...</a><br/></td></tr>
<tr class="separator:ga1df7d98bd6097267167a028bf2f1c254"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock Enable - FIFO Latency, fabric, DataPath,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>full-rate, output register</p>
<p>This register contains bits for various clock enable options of the ADC. Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga615621d488b4d98a970e055b9eeb284c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga615621d488b4d98a970e055b9eeb284c">XRFDC_CLK_EN_CAL_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga615621d488b4d98a970e055b9eeb284c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Output Register clock.  <a href="group___overview.html#ga615621d488b4d98a970e055b9eeb284c">More...</a><br/></td></tr>
<tr class="separator:ga615621d488b4d98a970e055b9eeb284c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01ea49ee2c3e06e98e75cff9bb60b4c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga01ea49ee2c3e06e98e75cff9bb60b4c2">XRFDC_CLK_EN_DIG_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga01ea49ee2c3e06e98e75cff9bb60b4c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable full-rate clock.  <a href="group___overview.html#ga01ea49ee2c3e06e98e75cff9bb60b4c2">More...</a><br/></td></tr>
<tr class="separator:ga01ea49ee2c3e06e98e75cff9bb60b4c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf4493bd634413b5dc96bc0068f79ca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaaf4493bd634413b5dc96bc0068f79ca1">XRFDC_CLK_EN_DP_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gaaf4493bd634413b5dc96bc0068f79ca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Data Path clock.  <a href="group___overview.html#gaaf4493bd634413b5dc96bc0068f79ca1">More...</a><br/></td></tr>
<tr class="separator:gaaf4493bd634413b5dc96bc0068f79ca1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe1045d38bb5eeb22ab7fc7ddb31a98b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafe1045d38bb5eeb22ab7fc7ddb31a98b">XRFDC_CLK_EN_FAB_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gafe1045d38bb5eeb22ab7fc7ddb31a98b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable fabric clock.  <a href="group___overview.html#gafe1045d38bb5eeb22ab7fc7ddb31a98b">More...</a><br/></td></tr>
<tr class="separator:gafe1045d38bb5eeb22ab7fc7ddb31a98b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d5715760b5f476b4a40c0a94a36d318"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d5715760b5f476b4a40c0a94a36d318">XRFDC_DAT_CLK_EN_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga2d5715760b5f476b4a40c0a94a36d318"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Path Clk enable.  <a href="group___overview.html#ga2d5715760b5f476b4a40c0a94a36d318">More...</a><br/></td></tr>
<tr class="separator:ga2d5715760b5f476b4a40c0a94a36d318"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0673e753f7017c347fdfea0815a4ad6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf0673e753f7017c347fdfea0815a4ad6">XRFDC_CLK_EN_LM_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gaf0673e753f7017c347fdfea0815a4ad6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable for FIFO Latency measurement clock.  <a href="group___overview.html#gaf0673e753f7017c347fdfea0815a4ad6">More...</a><br/></td></tr>
<tr class="separator:gaf0673e753f7017c347fdfea0815a4ad6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Debug reset - FIFO Latency, fabric, DataPath,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>full-rate, output register</p>
<p>This register contains bits for various Debug reset options of the ADC. Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga501bd80a90249106e43d3c317e4a76ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga501bd80a90249106e43d3c317e4a76ff">XRFDC_DBG_RST_CAL_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga501bd80a90249106e43d3c317e4a76ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset clk_cal clock domain.  <a href="group___overview.html#ga501bd80a90249106e43d3c317e4a76ff">More...</a><br/></td></tr>
<tr class="separator:ga501bd80a90249106e43d3c317e4a76ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f8885919161a822d89fe82791906683"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2f8885919161a822d89fe82791906683">XRFDC_DBG_RST_DP_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga2f8885919161a822d89fe82791906683"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset data path clock domain.  <a href="group___overview.html#ga2f8885919161a822d89fe82791906683">More...</a><br/></td></tr>
<tr class="separator:ga2f8885919161a822d89fe82791906683"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98ed4c354613a287d466f0db31d84ecb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga98ed4c354613a287d466f0db31d84ecb">XRFDC_DBG_RST_FAB_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga98ed4c354613a287d466f0db31d84ecb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset clock fabric clock domain.  <a href="group___overview.html#ga98ed4c354613a287d466f0db31d84ecb">More...</a><br/></td></tr>
<tr class="separator:ga98ed4c354613a287d466f0db31d84ecb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dd6b9de28ffebadb0a8e90e4b698834"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2dd6b9de28ffebadb0a8e90e4b698834">XRFDC_DBG_RST_DIG_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga2dd6b9de28ffebadb0a8e90e4b698834"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset clk_dig clock domain.  <a href="group___overview.html#ga2dd6b9de28ffebadb0a8e90e4b698834">More...</a><br/></td></tr>
<tr class="separator:ga2dd6b9de28ffebadb0a8e90e4b698834"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47f01c677b522f4ea04281e984e8b006"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga47f01c677b522f4ea04281e984e8b006">XRFDC_DBG_RST_DRP_CAL_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga47f01c677b522f4ea04281e984e8b006"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset subadc-drp register on clock cal.  <a href="group___overview.html#ga47f01c677b522f4ea04281e984e8b006">More...</a><br/></td></tr>
<tr class="separator:ga47f01c677b522f4ea04281e984e8b006"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga494a7efc6a46966372eeb30db339fe81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga494a7efc6a46966372eeb30db339fe81">XRFDC_DBG_RST_LM_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga494a7efc6a46966372eeb30db339fe81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset FIFO Latency measurement clock domain.  <a href="group___overview.html#ga494a7efc6a46966372eeb30db339fe81">More...</a><br/></td></tr>
<tr class="separator:ga494a7efc6a46966372eeb30db339fe81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Fabric rate - Fabric data rate for read and write</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for read and write fabric data rate for ADC.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga6f9c74a5cf9855427fce9f855c1d38ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6f9c74a5cf9855427fce9f855c1d38ea">XRFDC_ADC_FAB_RATE_WR_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga6f9c74a5cf9855427fce9f855c1d38ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Write Number of Words per clock.  <a href="group___overview.html#ga6f9c74a5cf9855427fce9f855c1d38ea">More...</a><br/></td></tr>
<tr class="separator:ga6f9c74a5cf9855427fce9f855c1d38ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e4f35e763faba17bdb7a126c05a618f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8e4f35e763faba17bdb7a126c05a618f">XRFDC_DAC_FAB_RATE_WR_MASK</a>&#160;&#160;&#160;0x0000001FU</td></tr>
<tr class="memdesc:ga8e4f35e763faba17bdb7a126c05a618f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO Write Number of Words per clock.  <a href="group___overview.html#ga8e4f35e763faba17bdb7a126c05a618f">More...</a><br/></td></tr>
<tr class="separator:ga8e4f35e763faba17bdb7a126c05a618f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbd3892f9d5e090ec4dd0a8aa8214cd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadbd3892f9d5e090ec4dd0a8aa8214cd8">XRFDC_ADC_FAB_RATE_RD_MASK</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:gadbd3892f9d5e090ec4dd0a8aa8214cd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO Read Number of Words per clock.  <a href="group___overview.html#gadbd3892f9d5e090ec4dd0a8aa8214cd8">More...</a><br/></td></tr>
<tr class="separator:gadbd3892f9d5e090ec4dd0a8aa8214cd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf190f93ad65c5accd97a9087a444d817"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf190f93ad65c5accd97a9087a444d817">XRFDC_DAC_FAB_RATE_RD_MASK</a>&#160;&#160;&#160;0x00001F00U</td></tr>
<tr class="memdesc:gaf190f93ad65c5accd97a9087a444d817"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO Read Number of Words per clock.  <a href="group___overview.html#gaf190f93ad65c5accd97a9087a444d817">More...</a><br/></td></tr>
<tr class="separator:gaf190f93ad65c5accd97a9087a444d817"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace3505a02363d9e4a1812d5f44038a2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gace3505a02363d9e4a1812d5f44038a2d">XRFDC_FAB_RATE_RD_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:gace3505a02363d9e4a1812d5f44038a2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fabric Read shift.  <a href="group___overview.html#gace3505a02363d9e4a1812d5f44038a2d">More...</a><br/></td></tr>
<tr class="separator:gace3505a02363d9e4a1812d5f44038a2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Fabric Offset - FIFO de-skew</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of Fabric Offset.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga94eb9927c0a6f63846ac5dcee4181589"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga94eb9927c0a6f63846ac5dcee4181589">XRFDC_FAB_RD_PTR_OFFST_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga94eb9927c0a6f63846ac5dcee4181589"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO read pointer offset for interface de-skew.  <a href="group___overview.html#ga94eb9927c0a6f63846ac5dcee4181589">More...</a><br/></td></tr>
<tr class="separator:ga94eb9927c0a6f63846ac5dcee4181589"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Fabric ISR - Interrupt status register for FIFO interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of margin-indicator and user-data overlap (overflow/underflow).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga416d93a62d317ddf5e6c9ba1283dc200"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga416d93a62d317ddf5e6c9ba1283dc200">XRFDC_FAB_ISR_USRDAT_OVR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga416d93a62d317ddf5e6c9ba1283dc200"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap- data written faster than read (overflow)  <a href="group___overview.html#ga416d93a62d317ddf5e6c9ba1283dc200">More...</a><br/></td></tr>
<tr class="separator:ga416d93a62d317ddf5e6c9ba1283dc200"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f842e216f52e45dc3e0922f8f86b2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga80f842e216f52e45dc3e0922f8f86b2d">XRFDC_FAB_ISR_USRDAT_UND_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga80f842e216f52e45dc3e0922f8f86b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap- data read faster than written (underflow)  <a href="group___overview.html#ga80f842e216f52e45dc3e0922f8f86b2d">More...</a><br/></td></tr>
<tr class="separator:ga80f842e216f52e45dc3e0922f8f86b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b5ee54b1ea1930f42367766f52dcafa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4b5ee54b1ea1930f42367766f52dcafa">XRFDC_FAB_ISR_USRDAT_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga4b5ee54b1ea1930f42367766f52dcafa"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap Mask.  <a href="group___overview.html#ga4b5ee54b1ea1930f42367766f52dcafa">More...</a><br/></td></tr>
<tr class="separator:ga4b5ee54b1ea1930f42367766f52dcafa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga297480579ef6286490cb37f3009c2db8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga297480579ef6286490cb37f3009c2db8">XRFDC_FAB_ISR_MARGIND_OVR_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga297480579ef6286490cb37f3009c2db8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal-indicator overlap (overflow)  <a href="group___overview.html#ga297480579ef6286490cb37f3009c2db8">More...</a><br/></td></tr>
<tr class="separator:ga297480579ef6286490cb37f3009c2db8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38fbfa7c037212f52991d588e18ff4d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga38fbfa7c037212f52991d588e18ff4d2">XRFDC_FAB_ISR_MARGIND_UND_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga38fbfa7c037212f52991d588e18ff4d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal-indicator overlap (underflow)  <a href="group___overview.html#ga38fbfa7c037212f52991d588e18ff4d2">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Fabric IMR - Interrupt mask register for FIFO interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of margin-indicator and user-data overlap (overflow/underflow).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga1a33c6eb70e40504ed2517a43fc297b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1a33c6eb70e40504ed2517a43fc297b0">XRFDC_FAB_IMR_USRDAT_OVR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga1a33c6eb70e40504ed2517a43fc297b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap- data written faster than read (overflow)  <a href="group___overview.html#ga1a33c6eb70e40504ed2517a43fc297b0">More...</a><br/></td></tr>
<tr class="separator:ga1a33c6eb70e40504ed2517a43fc297b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga650dfaea352a516fcc382707cc00826c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga650dfaea352a516fcc382707cc00826c">XRFDC_FAB_IMR_USRDAT_UND_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga650dfaea352a516fcc382707cc00826c"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap- data read faster than written (underflow)  <a href="group___overview.html#ga650dfaea352a516fcc382707cc00826c">More...</a><br/></td></tr>
<tr class="separator:ga650dfaea352a516fcc382707cc00826c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfc0ea1d71cfb685f5b9569e3918c755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacfc0ea1d71cfb685f5b9569e3918c755">XRFDC_FAB_IMR_USRDAT_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gacfc0ea1d71cfb685f5b9569e3918c755"><td class="mdescLeft">&#160;</td><td class="mdescRight">User-data overlap Mask.  <a href="group___overview.html#gacfc0ea1d71cfb685f5b9569e3918c755">More...</a><br/></td></tr>
<tr class="separator:gacfc0ea1d71cfb685f5b9569e3918c755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c72c1073d9c266babfe3670cc545bb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3c72c1073d9c266babfe3670cc545bb3">XRFDC_FAB_IMR_MARGIND_OVR_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga3c72c1073d9c266babfe3670cc545bb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal-indicator overlap (overflow)  <a href="group___overview.html#ga3c72c1073d9c266babfe3670cc545bb3">More...</a><br/></td></tr>
<tr class="separator:ga3c72c1073d9c266babfe3670cc545bb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaebdb7e951d46019d647fd872f2749b48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaebdb7e951d46019d647fd872f2749b48">XRFDC_FAB_IMR_MARGIND_UND_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaebdb7e951d46019d647fd872f2749b48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal-indicator overlap (underflow)  <a href="group___overview.html#gaebdb7e951d46019d647fd872f2749b48">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Update Dynamic - Trigger a dynamic update event</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of update event for slice, nco, qmc and coarse delay.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga3280baae4fc36d8025ff9cb65661d2b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3280baae4fc36d8025ff9cb65661d2b3">XRFDC_UPDT_EVNT_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga3280baae4fc36d8025ff9cb65661d2b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Update event mask.  <a href="group___overview.html#ga3280baae4fc36d8025ff9cb65661d2b3">More...</a><br/></td></tr>
<tr class="separator:ga3280baae4fc36d8025ff9cb65661d2b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a435f6aa2c95eb7959c54c942acf8f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7a435f6aa2c95eb7959c54c942acf8f7">XRFDC_UPDT_EVNT_SLICE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga7a435f6aa2c95eb7959c54c942acf8f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger a slice update event apply to _DCONFIG reg.  <a href="group___overview.html#ga7a435f6aa2c95eb7959c54c942acf8f7">More...</a><br/></td></tr>
<tr class="separator:ga7a435f6aa2c95eb7959c54c942acf8f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68255c917fc740033dffa4350ada6418"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga68255c917fc740033dffa4350ada6418">XRFDC_UPDT_EVNT_NCO_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga68255c917fc740033dffa4350ada6418"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger a update event apply to NCO_DCONFIG reg.  <a href="group___overview.html#ga68255c917fc740033dffa4350ada6418">More...</a><br/></td></tr>
<tr class="separator:ga68255c917fc740033dffa4350ada6418"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02758b59aa7200d893ad82cc536c9e82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga02758b59aa7200d893ad82cc536c9e82">XRFDC_UPDT_EVNT_QMC_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga02758b59aa7200d893ad82cc536c9e82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger a update event apply to QMC_DCONFIG reg.  <a href="group___overview.html#ga02758b59aa7200d893ad82cc536c9e82">More...</a><br/></td></tr>
<tr class="separator:ga02758b59aa7200d893ad82cc536c9e82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39761862ad6db5e8166c48e825d0599a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga39761862ad6db5e8166c48e825d0599a">XRFDC_ADC_UPDT_CRSE_DLY_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga39761862ad6db5e8166c48e825d0599a"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Trigger a update event apply to Coarse delay_DCONFIG reg.  <a href="group___overview.html#ga39761862ad6db5e8166c48e825d0599a">More...</a><br/></td></tr>
<tr class="separator:ga39761862ad6db5e8166c48e825d0599a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf37cda3ef6fa2358172e65fcce3f82cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf37cda3ef6fa2358172e65fcce3f82cc">XRFDC_DAC_UPDT_CRSE_DLY_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaf37cda3ef6fa2358172e65fcce3f82cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Trigger a update event apply to Coarse delay_DCONFIG reg.  <a href="group___overview.html#gaf37cda3ef6fa2358172e65fcce3f82cc">More...</a><br/></td></tr>
<tr class="separator:gaf37cda3ef6fa2358172e65fcce3f82cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Latency control - Config registers for FIFO Latency measurement</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of FIFO Latency ctrl for disable, restart and set fifo latency measurement.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaa0ddea16d50adfe2026d42d1e3bdc808"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa0ddea16d50adfe2026d42d1e3bdc808">XRFDC_FIFO_LTNCY_PRD_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gaa0ddea16d50adfe2026d42d1e3bdc808"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set FIFO Latency measurement period.  <a href="group___overview.html#gaa0ddea16d50adfe2026d42d1e3bdc808">More...</a><br/></td></tr>
<tr class="separator:gaa0ddea16d50adfe2026d42d1e3bdc808"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b7d8d83a9a7f26770dde31fb6e6d39c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7b7d8d83a9a7f26770dde31fb6e6d39c">XRFDC_FIFO_LTNCY_RESTRT_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7b7d8d83a9a7f26770dde31fb6e6d39c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Restart FIFO Latency measurement.  <a href="group___overview.html#ga7b7d8d83a9a7f26770dde31fb6e6d39c">More...</a><br/></td></tr>
<tr class="separator:ga7b7d8d83a9a7f26770dde31fb6e6d39c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6052385a44f60cf80225e4314cfd7c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac6052385a44f60cf80225e4314cfd7c5">XRFDC_FIFO_LTNCY_DIS_MASK</a>&#160;&#160;&#160;0x000000010U</td></tr>
<tr class="memdesc:gac6052385a44f60cf80225e4314cfd7c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable FIFO Latency measurement.  <a href="group___overview.html#gac6052385a44f60cf80225e4314cfd7c5">More...</a><br/></td></tr>
<tr class="separator:gac6052385a44f60cf80225e4314cfd7c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Decode ISR - ISR for Decoder Interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga9eae17c3d7faff770b567202a98e8bb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9eae17c3d7faff770b567202a98e8bb3">XRFDC_DEC_ISR_SUBADC_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga9eae17c3d7faff770b567202a98e8bb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc decoder Mask  <a href="group___overview.html#ga9eae17c3d7faff770b567202a98e8bb3">More...</a><br/></td></tr>
<tr class="separator:ga9eae17c3d7faff770b567202a98e8bb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga328563cf6a29be48272adb136cc27e56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga328563cf6a29be48272adb136cc27e56">XRFDC_DEC_ISR_SUBADC0_UND_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga328563cf6a29be48272adb136cc27e56"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0 decoder underflow range  <a href="group___overview.html#ga328563cf6a29be48272adb136cc27e56">More...</a><br/></td></tr>
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<tr class="memitem:ga7d4743f8292bf7c71ce7c4631cbe9d74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7d4743f8292bf7c71ce7c4631cbe9d74">XRFDC_DEC_ISR_SUBADC0_OVR_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga7d4743f8292bf7c71ce7c4631cbe9d74"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0 decoder overflow range  <a href="group___overview.html#ga7d4743f8292bf7c71ce7c4631cbe9d74">More...</a><br/></td></tr>
<tr class="separator:ga7d4743f8292bf7c71ce7c4631cbe9d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga118db55b3bc8636851f808d7a7a488b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga118db55b3bc8636851f808d7a7a488b1">XRFDC_DEC_ISR_SUBADC1_UND_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga118db55b3bc8636851f808d7a7a488b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1 decoder underflow range  <a href="group___overview.html#ga118db55b3bc8636851f808d7a7a488b1">More...</a><br/></td></tr>
<tr class="separator:ga118db55b3bc8636851f808d7a7a488b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c2e5d7ab148c9de12f5c3a80cb9cbd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2c2e5d7ab148c9de12f5c3a80cb9cbd2">XRFDC_DEC_ISR_SUBADC1_OVR_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga2c2e5d7ab148c9de12f5c3a80cb9cbd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1 decoder overflow range  <a href="group___overview.html#ga2c2e5d7ab148c9de12f5c3a80cb9cbd2">More...</a><br/></td></tr>
<tr class="separator:ga2c2e5d7ab148c9de12f5c3a80cb9cbd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab136cea49ad6cbafb266521bc66d265"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaab136cea49ad6cbafb266521bc66d265">XRFDC_DEC_ISR_SUBADC2_UND_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gaab136cea49ad6cbafb266521bc66d265"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2 decoder underflow range  <a href="group___overview.html#gaab136cea49ad6cbafb266521bc66d265">More...</a><br/></td></tr>
<tr class="separator:gaab136cea49ad6cbafb266521bc66d265"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02ce057ff37b541f3018fccf1ed4178a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga02ce057ff37b541f3018fccf1ed4178a">XRFDC_DEC_ISR_SUBADC2_OVR_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga02ce057ff37b541f3018fccf1ed4178a"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2 decoder overflow range  <a href="group___overview.html#ga02ce057ff37b541f3018fccf1ed4178a">More...</a><br/></td></tr>
<tr class="separator:ga02ce057ff37b541f3018fccf1ed4178a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74e652d3575448d7108d8b07790f14cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga74e652d3575448d7108d8b07790f14cd">XRFDC_DEC_ISR_SUBADC3_UND_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga74e652d3575448d7108d8b07790f14cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3 decoder underflow range  <a href="group___overview.html#ga74e652d3575448d7108d8b07790f14cd">More...</a><br/></td></tr>
<tr class="separator:ga74e652d3575448d7108d8b07790f14cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6caad984b393c675dd76a096e25b532f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6caad984b393c675dd76a096e25b532f">XRFDC_DEC_ISR_SUBADC3_OVR_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga6caad984b393c675dd76a096e25b532f"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3 decoder overflow range  <a href="group___overview.html#ga6caad984b393c675dd76a096e25b532f">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Decode IMR - IMR for Decoder Interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf4cd3ff3e24641b3bb00576a34a0b04d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf4cd3ff3e24641b3bb00576a34a0b04d">XRFDC_DEC_IMR_SUBADC0_UND_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaf4cd3ff3e24641b3bb00576a34a0b04d"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0 decoder underflow range  <a href="group___overview.html#gaf4cd3ff3e24641b3bb00576a34a0b04d">More...</a><br/></td></tr>
<tr class="separator:gaf4cd3ff3e24641b3bb00576a34a0b04d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03d56a7fcf3ed90e2e1e1bfd6f59bb7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03d56a7fcf3ed90e2e1e1bfd6f59bb7a">XRFDC_DEC_IMR_SUBADC0_OVR_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga03d56a7fcf3ed90e2e1e1bfd6f59bb7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc0 decoder overflow range  <a href="group___overview.html#ga03d56a7fcf3ed90e2e1e1bfd6f59bb7a">More...</a><br/></td></tr>
<tr class="separator:ga03d56a7fcf3ed90e2e1e1bfd6f59bb7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4aaf7ca54d82dabd8dcde75bb2795f32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4aaf7ca54d82dabd8dcde75bb2795f32">XRFDC_DEC_IMR_SUBADC1_UND_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga4aaf7ca54d82dabd8dcde75bb2795f32"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1 decoder underflow range  <a href="group___overview.html#ga4aaf7ca54d82dabd8dcde75bb2795f32">More...</a><br/></td></tr>
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<tr class="memitem:ga7763d1f4d4c0c9ef7637067b0829e0ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7763d1f4d4c0c9ef7637067b0829e0ac">XRFDC_DEC_IMR_SUBADC1_OVR_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7763d1f4d4c0c9ef7637067b0829e0ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc1 decoder overflow range  <a href="group___overview.html#ga7763d1f4d4c0c9ef7637067b0829e0ac">More...</a><br/></td></tr>
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<tr class="memitem:ga5b867c128506a3707cb0a96da1ec92df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5b867c128506a3707cb0a96da1ec92df">XRFDC_DEC_IMR_SUBADC2_UND_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga5b867c128506a3707cb0a96da1ec92df"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2 decoder underflow range  <a href="group___overview.html#ga5b867c128506a3707cb0a96da1ec92df">More...</a><br/></td></tr>
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<tr class="memitem:ga620fac8b277561df4058d572e00b082d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga620fac8b277561df4058d572e00b082d">XRFDC_DEC_IMR_SUBADC2_OVR_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga620fac8b277561df4058d572e00b082d"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc2 decoder overflow range  <a href="group___overview.html#ga620fac8b277561df4058d572e00b082d">More...</a><br/></td></tr>
<tr class="separator:ga620fac8b277561df4058d572e00b082d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae57507c44bb48929ebdf873af8b995a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae57507c44bb48929ebdf873af8b995a8">XRFDC_DEC_IMR_SUBADC3_UND_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gae57507c44bb48929ebdf873af8b995a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3 decoder underflow range  <a href="group___overview.html#gae57507c44bb48929ebdf873af8b995a8">More...</a><br/></td></tr>
<tr class="separator:gae57507c44bb48929ebdf873af8b995a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga938d9f03f03c6e532c85e5fe487a35ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga938d9f03f03c6e532c85e5fe487a35ec">XRFDC_DEC_IMR_SUBADC3_OVR_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga938d9f03f03c6e532c85e5fe487a35ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">subadc3 decoder overflow range  <a href="group___overview.html#ga938d9f03f03c6e532c85e5fe487a35ec">More...</a><br/></td></tr>
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<tr class="memitem:gac532c38d799b91d391258e5ce3de9d8e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac532c38d799b91d391258e5ce3de9d8e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_DEC_IMR_MASK</b>&#160;&#160;&#160;0x000000FFU</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DataPath (DAC)- FIFO Latency, Image Reject Filter, Mode,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for DataPath latency, Image Reject Filter and the Mode for the DAC.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga13267e1dcb9a2d818b77cfd625ddbc1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga13267e1dcb9a2d818b77cfd625ddbc1f">XRFDC_DATAPATH_MODE_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga13267e1dcb9a2d818b77cfd625ddbc1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DataPath Mode.  <a href="group___overview.html#ga13267e1dcb9a2d818b77cfd625ddbc1f">More...</a><br/></td></tr>
<tr class="separator:ga13267e1dcb9a2d818b77cfd625ddbc1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09e759e03c7ab457cde350dcbac860b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga09e759e03c7ab457cde350dcbac860b6">XRFDC_DATAPATH_IMR_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga09e759e03c7ab457cde350dcbac860b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IMR Mode.  <a href="group___overview.html#ga09e759e03c7ab457cde350dcbac860b6">More...</a><br/></td></tr>
<tr class="separator:ga09e759e03c7ab457cde350dcbac860b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9371bedeba445bf48970e67ef024494e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9371bedeba445bf48970e67ef024494e">XRFDC_DATAPATH_LATENCY_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9371bedeba445bf48970e67ef024494e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DataPath Latency.  <a href="group___overview.html#ga9371bedeba445bf48970e67ef024494e">More...</a><br/></td></tr>
<tr class="separator:ga9371bedeba445bf48970e67ef024494e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3cf9f3af0019d328ea8ba466921a8fcb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3cf9f3af0019d328ea8ba466921a8fcb">XRFDC_DATAPATH_IMR_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:ga3cf9f3af0019d328ea8ba466921a8fcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">IMR Mode shift.  <a href="group___overview.html#ga3cf9f3af0019d328ea8ba466921a8fcb">More...</a><br/></td></tr>
<tr class="separator:ga3cf9f3af0019d328ea8ba466921a8fcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DataPath ISR - ISR for Data Path interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga47aba762f53a541a888b1ca87620961f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga47aba762f53a541a888b1ca87620961f">XRFDC_ADC_DAT_PATH_ISR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga47aba762f53a541a888b1ca87620961f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Data Path Overflow.  <a href="group___overview.html#ga47aba762f53a541a888b1ca87620961f">More...</a><br/></td></tr>
<tr class="separator:ga47aba762f53a541a888b1ca87620961f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa9a450174d1e4a8064167eb226826c84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa9a450174d1e4a8064167eb226826c84">XRFDC_DAC_DAT_PATH_ISR_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaa9a450174d1e4a8064167eb226826c84"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Data Path Overflow.  <a href="group___overview.html#gaa9a450174d1e4a8064167eb226826c84">More...</a><br/></td></tr>
<tr class="separator:gaa9a450174d1e4a8064167eb226826c84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad92d80b5062e0cac6c42a69b92d2fdf9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad92d80b5062e0cac6c42a69b92d2fdf9">XRFDC_DAT_ISR_DECI_IPATH_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gad92d80b5062e0cac6c42a69b92d2fdf9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decimation I-Path overflow for stages 0,1,2.  <a href="group___overview.html#gad92d80b5062e0cac6c42a69b92d2fdf9">More...</a><br/></td></tr>
<tr class="separator:gad92d80b5062e0cac6c42a69b92d2fdf9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cdf027d2c7a098c7b275f2ad0217a07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6cdf027d2c7a098c7b275f2ad0217a07">XRFDC_DAT_ISR_INTR_QPATH_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga6cdf027d2c7a098c7b275f2ad0217a07"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interpolation Q-Path overflow for stages 0,1,2.  <a href="group___overview.html#ga6cdf027d2c7a098c7b275f2ad0217a07">More...</a><br/></td></tr>
<tr class="separator:ga6cdf027d2c7a098c7b275f2ad0217a07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga959060cdc6bfccf95a8d76325b6a9d6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga959060cdc6bfccf95a8d76325b6a9d6f">XRFDC_DAT_ISR_QMC_GAIN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga959060cdc6bfccf95a8d76325b6a9d6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC Gain/Phase overflow.  <a href="group___overview.html#ga959060cdc6bfccf95a8d76325b6a9d6f">More...</a><br/></td></tr>
<tr class="separator:ga959060cdc6bfccf95a8d76325b6a9d6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41efa947ca0981edb12fb3f473ac2866"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga41efa947ca0981edb12fb3f473ac2866">XRFDC_DAT_ISR_QMC_OFFST_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga41efa947ca0981edb12fb3f473ac2866"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC offset overflow.  <a href="group___overview.html#ga41efa947ca0981edb12fb3f473ac2866">More...</a><br/></td></tr>
<tr class="separator:ga41efa947ca0981edb12fb3f473ac2866"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2bf4fc9291e59595846e1689b5c93f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae2bf4fc9291e59595846e1689b5c93f5">XRFDC_DAC_DAT_ISR_INVSINC_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:gae2bf4fc9291e59595846e1689b5c93f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Inverse-Sinc offset overflow.  <a href="group___overview.html#gae2bf4fc9291e59595846e1689b5c93f5">More...</a><br/></td></tr>
<tr class="separator:gae2bf4fc9291e59595846e1689b5c93f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DataPath IMR - IMR for Data Path interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.</p>
<p>Inverse sinc overflow, Datapath Scaling, Interpolation I and Q, IMR, and Even Nyquist Zone overflow Mixer I and Q over/underflow. Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaa40610e65de797daef844a48cb5787b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa40610e65de797daef844a48cb5787b5">XRFDC_DAT_IMR_DECI_IPATH_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gaa40610e65de797daef844a48cb5787b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decimation I-Path overflow for stages 0,1,2.  <a href="group___overview.html#gaa40610e65de797daef844a48cb5787b5">More...</a><br/></td></tr>
<tr class="separator:gaa40610e65de797daef844a48cb5787b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36be1b1af9ed97d172b828486f5617e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga36be1b1af9ed97d172b828486f5617e1">XRFDC_DAT_IMR_INTR_QPATH_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga36be1b1af9ed97d172b828486f5617e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interpolation Q-Path overflow for stages 0,1,2.  <a href="group___overview.html#ga36be1b1af9ed97d172b828486f5617e1">More...</a><br/></td></tr>
<tr class="separator:ga36be1b1af9ed97d172b828486f5617e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee5bd87366d518baea52a7811289b74e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaee5bd87366d518baea52a7811289b74e">XRFDC_DAT_IMR_QMC_GAIN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gaee5bd87366d518baea52a7811289b74e"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC Gain/Phase overflow.  <a href="group___overview.html#gaee5bd87366d518baea52a7811289b74e">More...</a><br/></td></tr>
<tr class="separator:gaee5bd87366d518baea52a7811289b74e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21a16db5b1ff9adf930ee8c4b1a2a695"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga21a16db5b1ff9adf930ee8c4b1a2a695">XRFDC_DAT_IMR_QMC_OFFST_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga21a16db5b1ff9adf930ee8c4b1a2a695"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC offset overflow.  <a href="group___overview.html#ga21a16db5b1ff9adf930ee8c4b1a2a695">More...</a><br/></td></tr>
<tr class="separator:ga21a16db5b1ff9adf930ee8c4b1a2a695"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f24aa57724c39de1fd0b485577a98d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6f24aa57724c39de1fd0b485577a98d1">XRFDC_DAC_DAT_IMR_INV_SINC_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga6f24aa57724c39de1fd0b485577a98d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Inverse Sinc overflow.  <a href="group___overview.html#ga6f24aa57724c39de1fd0b485577a98d1">More...</a><br/></td></tr>
<tr class="separator:ga6f24aa57724c39de1fd0b485577a98d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga779fbf59b0d525dd938b6790fe955037"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga779fbf59b0d525dd938b6790fe955037">XRFDC_DAC_DAT_IMR_MXR_HLF_I_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga779fbf59b0d525dd938b6790fe955037"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over or under flow mixer (Mixer half I)  <a href="group___overview.html#ga779fbf59b0d525dd938b6790fe955037">More...</a><br/></td></tr>
<tr class="separator:ga779fbf59b0d525dd938b6790fe955037"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93e437234b36bde19d586bd290cac6e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga93e437234b36bde19d586bd290cac6e5">XRFDC_DAC_DAT_IMR_MXR_HLF_Q_MASK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga93e437234b36bde19d586bd290cac6e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over or under flow mixer (Mixer half Q)  <a href="group___overview.html#ga93e437234b36bde19d586bd290cac6e5">More...</a><br/></td></tr>
<tr class="separator:ga93e437234b36bde19d586bd290cac6e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e42f0bf847d6ec5756c98500517e3bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9e42f0bf847d6ec5756c98500517e3bd">XRFDC_DAC_DAT_IMR_DP_SCALE_MASK</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:ga9e42f0bf847d6ec5756c98500517e3bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">DataPath Scaling overflow.  <a href="group___overview.html#ga9e42f0bf847d6ec5756c98500517e3bd">More...</a><br/></td></tr>
<tr class="separator:ga9e42f0bf847d6ec5756c98500517e3bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaea19ce8f831b462faea429737f73fb94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaea19ce8f831b462faea429737f73fb94">XRFDC_DAC_DAT_IMR_INTR_IPATH3_MASK</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:gaea19ce8f831b462faea429737f73fb94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interpolation I-Path overflow for stage 3.  <a href="group___overview.html#gaea19ce8f831b462faea429737f73fb94">More...</a><br/></td></tr>
<tr class="separator:gaea19ce8f831b462faea429737f73fb94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d9b014486a745576d6f1bedd8355ccc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d9b014486a745576d6f1bedd8355ccc">XRFDC_DAC_DAT_IMR_INTR_QPATH3_MASK</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:ga2d9b014486a745576d6f1bedd8355ccc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interpolation Q-Path overflow for stage 3.  <a href="group___overview.html#ga2d9b014486a745576d6f1bedd8355ccc">More...</a><br/></td></tr>
<tr class="separator:ga2d9b014486a745576d6f1bedd8355ccc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0371e8e3754a1dc9a53d22ce0595dfc3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0371e8e3754a1dc9a53d22ce0595dfc3">XRFDC_DAC_DAT_IMR_IMR_OV_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:ga0371e8e3754a1dc9a53d22ce0595dfc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">IMR overflow.  <a href="group___overview.html#ga0371e8e3754a1dc9a53d22ce0595dfc3">More...</a><br/></td></tr>
<tr class="separator:ga0371e8e3754a1dc9a53d22ce0595dfc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac41eb51de4b2f7d848082a07ba12641b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac41eb51de4b2f7d848082a07ba12641b">XRFDC_DAC_DAT_IMR_INV_SINC_EVEN_NYQ_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gac41eb51de4b2f7d848082a07ba12641b"><td class="mdescLeft">&#160;</td><td class="mdescRight">2nd Nyquist Zone Inverse SINC overflow  <a href="group___overview.html#gac41eb51de4b2f7d848082a07ba12641b">More...</a><br/></td></tr>
<tr class="separator:gac41eb51de4b2f7d848082a07ba12641b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa085307ab0a26c9ae85465854bc4d3be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa085307ab0a26c9ae85465854bc4d3be">XRFDC_ADC_DAT_IMR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaa085307ab0a26c9ae85465854bc4d3be"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC DataPath mask.  <a href="group___overview.html#gaa085307ab0a26c9ae85465854bc4d3be">More...</a><br/></td></tr>
<tr class="separator:gaa085307ab0a26c9ae85465854bc4d3be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae65f2df5cca1c653b02d8449ea17408d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae65f2df5cca1c653b02d8449ea17408d">XRFDC_DAC_DAT_IMR_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gae65f2df5cca1c653b02d8449ea17408d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC DataPath mask.  <a href="group___overview.html#gae65f2df5cca1c653b02d8449ea17408d">More...</a><br/></td></tr>
<tr class="separator:gae65f2df5cca1c653b02d8449ea17408d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO IMR - FIFO for Data Path interface</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits of FIFO over/underflows Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gae751d238493a1541e9f0a33b42c62cfd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae751d238493a1541e9f0a33b42c62cfd">XRFDC_FIFO_USRD_OF_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gae751d238493a1541e9f0a33b42c62cfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">User data overflow.  <a href="group___overview.html#gae751d238493a1541e9f0a33b42c62cfd">More...</a><br/></td></tr>
<tr class="separator:gae751d238493a1541e9f0a33b42c62cfd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga451cd0d1f67a072c5b822ebfdecc424e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga451cd0d1f67a072c5b822ebfdecc424e">XRFDC_FIFO_USRD_UF_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga451cd0d1f67a072c5b822ebfdecc424e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User data underflow.  <a href="group___overview.html#ga451cd0d1f67a072c5b822ebfdecc424e">More...</a><br/></td></tr>
<tr class="separator:ga451cd0d1f67a072c5b822ebfdecc424e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d13208faff862b995f3d76437c36497"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9d13208faff862b995f3d76437c36497">XRFDC_FIFO_MRGN_OF_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga9d13208faff862b995f3d76437c36497"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal overflow.  <a href="group___overview.html#ga9d13208faff862b995f3d76437c36497">More...</a><br/></td></tr>
<tr class="separator:ga9d13208faff862b995f3d76437c36497"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07882dfd45e3fa1b9db30d07814c781e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga07882dfd45e3fa1b9db30d07814c781e">XRFDC_FIFO_MRGN_UF_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga07882dfd45e3fa1b9db30d07814c781e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Marginal underflow.  <a href="group___overview.html#ga07882dfd45e3fa1b9db30d07814c781e">More...</a><br/></td></tr>
<tr class="separator:ga07882dfd45e3fa1b9db30d07814c781e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc19f5076f536d8d40172a149b1fb3c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafc19f5076f536d8d40172a149b1fb3c3">XRFDC_FIFO_ACTL_OF_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gafc19f5076f536d8d40172a149b1fb3c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Actual overflow.  <a href="group___overview.html#gafc19f5076f536d8d40172a149b1fb3c3">More...</a><br/></td></tr>
<tr class="separator:gafc19f5076f536d8d40172a149b1fb3c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7875334804ca6dcdd59273cef4566b55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7875334804ca6dcdd59273cef4566b55">XRFDC_FIFO_ACTL_UF_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga7875334804ca6dcdd59273cef4566b55"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Actual underflow.  <a href="group___overview.html#ga7875334804ca6dcdd59273cef4566b55">More...</a><br/></td></tr>
<tr class="separator:ga7875334804ca6dcdd59273cef4566b55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga349140be38d28c8b5a0c70f85b510fb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga349140be38d28c8b5a0c70f85b510fb3">XRFDC_DAC_FIFO_IMR_SUPP_MASK</a>&#160;&#160;&#160;0x00000030U</td></tr>
<tr class="memdesc:ga349140be38d28c8b5a0c70f85b510fb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO Mask.  <a href="group___overview.html#ga349140be38d28c8b5a0c70f85b510fb3">More...</a><br/></td></tr>
<tr class="separator:ga349140be38d28c8b5a0c70f85b510fb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6bf6804b06fe2b57d697f33881e96a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad6bf6804b06fe2b57d697f33881e96a3">XRFDC_DAC_FIFO_IMR_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:gad6bf6804b06fe2b57d697f33881e96a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO Mask.  <a href="group___overview.html#gad6bf6804b06fe2b57d697f33881e96a3">More...</a><br/></td></tr>
<tr class="separator:gad6bf6804b06fe2b57d697f33881e96a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Decimation Config - Decimation control</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure the decimation in terms of the type of data.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga5370ff85740b209be6e094d4a73816a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5370ff85740b209be6e094d4a73816a7">XRFDC_DEC_CFG_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga5370ff85740b209be6e094d4a73816a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">ChannelA (2GSPS real data from Mixer I output)  <a href="group___overview.html#ga5370ff85740b209be6e094d4a73816a7">More...</a><br/></td></tr>
<tr class="separator:ga5370ff85740b209be6e094d4a73816a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab00c7a73030b63d1044c3984f28c9f3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab00c7a73030b63d1044c3984f28c9f3e">XRFDC_DEC_CFG_CHA_MASK</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gab00c7a73030b63d1044c3984f28c9f3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ChannelA(I)  <a href="group___overview.html#gab00c7a73030b63d1044c3984f28c9f3e">More...</a><br/></td></tr>
<tr class="separator:gab00c7a73030b63d1044c3984f28c9f3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8615d7b0cd24bccc3dbbc9ec8535328"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad8615d7b0cd24bccc3dbbc9ec8535328">XRFDC_DEC_CFG_CHB_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gad8615d7b0cd24bccc3dbbc9ec8535328"><td class="mdescLeft">&#160;</td><td class="mdescRight">ChannelB (2GSPS real data from Mixer Q output)  <a href="group___overview.html#gad8615d7b0cd24bccc3dbbc9ec8535328">More...</a><br/></td></tr>
<tr class="separator:gad8615d7b0cd24bccc3dbbc9ec8535328"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8554eb910540c87a9f5d85f484ff731"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae8554eb910540c87a9f5d85f484ff731">XRFDC_DEC_CFG_IQ_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gae8554eb910540c87a9f5d85f484ff731"><td class="mdescLeft">&#160;</td><td class="mdescRight">IQ-2GSPS.  <a href="group___overview.html#gae8554eb910540c87a9f5d85f484ff731">More...</a><br/></td></tr>
<tr class="separator:gae8554eb910540c87a9f5d85f484ff731"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33186feb8ac7f37e8bac96106471898e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga33186feb8ac7f37e8bac96106471898e">XRFDC_DEC_CFG_4GSPS_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga33186feb8ac7f37e8bac96106471898e"><td class="mdescLeft">&#160;</td><td class="mdescRight">4GSPS may be I or Q or Real depending on high level block config  <a href="group___overview.html#ga33186feb8ac7f37e8bac96106471898e">More...</a><br/></td></tr>
<tr class="separator:ga33186feb8ac7f37e8bac96106471898e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Decimation Mode - Decimation Rate</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configures the decimation rate.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gae5fcbb9fcf48b568fc10a78aa092b946"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae5fcbb9fcf48b568fc10a78aa092b946">XRFDC_DEC_MOD_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gae5fcbb9fcf48b568fc10a78aa092b946"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decimation mode Mask.  <a href="group___overview.html#gae5fcbb9fcf48b568fc10a78aa092b946">More...</a><br/></td></tr>
<tr class="separator:gae5fcbb9fcf48b568fc10a78aa092b946"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4c7a6ddb59d39721393b3c7ec78ee55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab4c7a6ddb59d39721393b3c7ec78ee55">XRFDC_DEC_MOD_MASK_EXT</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:gab4c7a6ddb59d39721393b3c7ec78ee55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decimation mode Mask.  <a href="group___overview.html#gab4c7a6ddb59d39721393b3c7ec78ee55">More...</a><br/></td></tr>
<tr class="separator:gab4c7a6ddb59d39721393b3c7ec78ee55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Mixer config0 - Configure I channel coarse mixer mode of operation</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set the output data sequence of I channel.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga885a3e14bed9b9d08d2175d1e7b358fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga885a3e14bed9b9d08d2175d1e7b358fb">XRFDC_MIX_CFG0_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:ga885a3e14bed9b9d08d2175d1e7b358fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer Config0 Mask.  <a href="group___overview.html#ga885a3e14bed9b9d08d2175d1e7b358fb">More...</a><br/></td></tr>
<tr class="separator:ga885a3e14bed9b9d08d2175d1e7b358fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecc1cdf9166daa7b8a2cd94d2f48ec2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaecc1cdf9166daa7b8a2cd94d2f48ec2f">XRFDC_MIX_I_DAT_WRD0_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gaecc1cdf9166daa7b8a2cd94d2f48ec2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[0] of I channel.  <a href="group___overview.html#gaecc1cdf9166daa7b8a2cd94d2f48ec2f">More...</a><br/></td></tr>
<tr class="separator:gaecc1cdf9166daa7b8a2cd94d2f48ec2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74563974ebd9b75fc241f1cf0c7ee8a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga74563974ebd9b75fc241f1cf0c7ee8a9">XRFDC_MIX_I_DAT_WRD1_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga74563974ebd9b75fc241f1cf0c7ee8a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[1] of I channel.  <a href="group___overview.html#ga74563974ebd9b75fc241f1cf0c7ee8a9">More...</a><br/></td></tr>
<tr class="separator:ga74563974ebd9b75fc241f1cf0c7ee8a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac299b0b2c3b83fa726a860ca4957ddf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac299b0b2c3b83fa726a860ca4957ddf2">XRFDC_MIX_I_DAT_WRD2_MASK</a>&#160;&#160;&#160;0x000001C0U</td></tr>
<tr class="memdesc:gac299b0b2c3b83fa726a860ca4957ddf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[2] of I channel.  <a href="group___overview.html#gac299b0b2c3b83fa726a860ca4957ddf2">More...</a><br/></td></tr>
<tr class="separator:gac299b0b2c3b83fa726a860ca4957ddf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga461becd9bfafd60d0bc79f44736d52af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga461becd9bfafd60d0bc79f44736d52af">XRFDC_MIX_I_DAT_WRD3_MASK</a>&#160;&#160;&#160;0x00000E00U</td></tr>
<tr class="memdesc:ga461becd9bfafd60d0bc79f44736d52af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[3] of I channel.  <a href="group___overview.html#ga461becd9bfafd60d0bc79f44736d52af">More...</a><br/></td></tr>
<tr class="separator:ga461becd9bfafd60d0bc79f44736d52af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Mixer config1 - Configure Q channel coarse mixer mode of operation</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set the output data sequence of Q channel.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gab0d9fb79a902668f0497bddda9d6f8a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab0d9fb79a902668f0497bddda9d6f8a3">XRFDC_MIX_CFG1_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:gab0d9fb79a902668f0497bddda9d6f8a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer Config0 Mask.  <a href="group___overview.html#gab0d9fb79a902668f0497bddda9d6f8a3">More...</a><br/></td></tr>
<tr class="separator:gab0d9fb79a902668f0497bddda9d6f8a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga403d8792824070fc160159e84ccc4d09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga403d8792824070fc160159e84ccc4d09">XRFDC_MIX_Q_DAT_WRD0_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga403d8792824070fc160159e84ccc4d09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[0] of Q channel.  <a href="group___overview.html#ga403d8792824070fc160159e84ccc4d09">More...</a><br/></td></tr>
<tr class="separator:ga403d8792824070fc160159e84ccc4d09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe61d1ba064b482e7477c56786fceb06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabe61d1ba064b482e7477c56786fceb06">XRFDC_MIX_Q_DAT_WRD1_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:gabe61d1ba064b482e7477c56786fceb06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[1] of Q channel.  <a href="group___overview.html#gabe61d1ba064b482e7477c56786fceb06">More...</a><br/></td></tr>
<tr class="separator:gabe61d1ba064b482e7477c56786fceb06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac15668a0a7cf5b91160ec199143fa444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac15668a0a7cf5b91160ec199143fa444">XRFDC_MIX_Q_DAT_WRD2_MASK</a>&#160;&#160;&#160;0x000001C0U</td></tr>
<tr class="memdesc:gac15668a0a7cf5b91160ec199143fa444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[2] of Q channel.  <a href="group___overview.html#gac15668a0a7cf5b91160ec199143fa444">More...</a><br/></td></tr>
<tr class="separator:gac15668a0a7cf5b91160ec199143fa444"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade1090b461bd7632e44adbaee38ae2af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gade1090b461bd7632e44adbaee38ae2af">XRFDC_MIX_Q_DAT_WRD3_MASK</a>&#160;&#160;&#160;0x00000E00U</td></tr>
<tr class="memdesc:gade1090b461bd7632e44adbaee38ae2af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output data word[3] of Q channel.  <a href="group___overview.html#gade1090b461bd7632e44adbaee38ae2af">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Mixer mode - Configure mixer mode of operation</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set NCO phases, NCO output scale and fine mixer multipliers.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga9c687208b0b553239dc95d8752e0f93e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9c687208b0b553239dc95d8752e0f93e">XRFDC_EN_I_IQ_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga9c687208b0b553239dc95d8752e0f93e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable fine mixer multipliers on IQ i/p for I output.  <a href="group___overview.html#ga9c687208b0b553239dc95d8752e0f93e">More...</a><br/></td></tr>
<tr class="separator:ga9c687208b0b553239dc95d8752e0f93e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51daa90a995744e8c846c0287f6689a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga51daa90a995744e8c846c0287f6689a3">XRFDC_EN_Q_IQ_MASK</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:ga51daa90a995744e8c846c0287f6689a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable fine mixer multipliers on IQ i/p for Q output.  <a href="group___overview.html#ga51daa90a995744e8c846c0287f6689a3">More...</a><br/></td></tr>
<tr class="separator:ga51daa90a995744e8c846c0287f6689a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabbbc3a97d82bec4822f938d5b1a1eec1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabbbc3a97d82bec4822f938d5b1a1eec1">XRFDC_FINE_MIX_SCALE_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gabbbc3a97d82bec4822f938d5b1a1eec1"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO output scale.  <a href="group___overview.html#gabbbc3a97d82bec4822f938d5b1a1eec1">More...</a><br/></td></tr>
<tr class="separator:gabbbc3a97d82bec4822f938d5b1a1eec1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16b20e441a95c0016a956166d31a2158"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga16b20e441a95c0016a956166d31a2158">XRFDC_SEL_I_IQ_MASK</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:ga16b20e441a95c0016a956166d31a2158"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select NCO phases for I output.  <a href="group___overview.html#ga16b20e441a95c0016a956166d31a2158">More...</a><br/></td></tr>
<tr class="separator:ga16b20e441a95c0016a956166d31a2158"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a68a0b557045661ebb961bff84f064b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4a68a0b557045661ebb961bff84f064b">XRFDC_SEL_Q_IQ_MASK</a>&#160;&#160;&#160;0x0000F000U</td></tr>
<tr class="memdesc:ga4a68a0b557045661ebb961bff84f064b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select NCO phases for Q output.  <a href="group___overview.html#ga4a68a0b557045661ebb961bff84f064b">More...</a><br/></td></tr>
<tr class="separator:ga4a68a0b557045661ebb961bff84f064b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cfeb8232dfda0affd5f164fe876949f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6cfeb8232dfda0affd5f164fe876949f">XRFDC_I_IQ_COS_MINSIN</a>&#160;&#160;&#160;0x00000C00U</td></tr>
<tr class="memdesc:ga6cfeb8232dfda0affd5f164fe876949f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select NCO phases for I output.  <a href="group___overview.html#ga6cfeb8232dfda0affd5f164fe876949f">More...</a><br/></td></tr>
<tr class="separator:ga6cfeb8232dfda0affd5f164fe876949f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb5fbe234ba7ddacab85e5419a382222"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadb5fbe234ba7ddacab85e5419a382222">XRFDC_Q_IQ_SIN_COS</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:gadb5fbe234ba7ddacab85e5419a382222"><td class="mdescLeft">&#160;</td><td class="mdescRight">Select NCO phases for Q output.  <a href="group___overview.html#gadb5fbe234ba7ddacab85e5419a382222">More...</a><br/></td></tr>
<tr class="separator:gadb5fbe234ba7ddacab85e5419a382222"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga891b57ba32606d2115b56da7020fd9c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga891b57ba32606d2115b56da7020fd9c5">XRFDC_MIXER_MODE_C2C_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga891b57ba32606d2115b56da7020fd9c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer mode C2C Mask.  <a href="group___overview.html#ga891b57ba32606d2115b56da7020fd9c5">More...</a><br/></td></tr>
<tr class="separator:ga891b57ba32606d2115b56da7020fd9c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b5324c4598dc81590ff5f0959805aee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7b5324c4598dc81590ff5f0959805aee">XRFDC_MIXER_MODE_R2C_MASK</a>&#160;&#160;&#160;0x00000005U</td></tr>
<tr class="memdesc:ga7b5324c4598dc81590ff5f0959805aee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer mode R2C Mask.  <a href="group___overview.html#ga7b5324c4598dc81590ff5f0959805aee">More...</a><br/></td></tr>
<tr class="separator:ga7b5324c4598dc81590ff5f0959805aee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab90dc5a5ae826344aef51e0c6e94f0e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab90dc5a5ae826344aef51e0c6e94f0e0">XRFDC_MIXER_MODE_C2R_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gab90dc5a5ae826344aef51e0c6e94f0e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer mode C2R Mask.  <a href="group___overview.html#gab90dc5a5ae826344aef51e0c6e94f0e0">More...</a><br/></td></tr>
<tr class="separator:gab90dc5a5ae826344aef51e0c6e94f0e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2e70de7b1bc13041c7e649c37c9d153"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae2e70de7b1bc13041c7e649c37c9d153">XRFDC_MIXER_MODE_OFF_MASK</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gae2e70de7b1bc13041c7e649c37c9d153"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mixer mode OFF Mask.  <a href="group___overview.html#gae2e70de7b1bc13041c7e649c37c9d153">More...</a><br/></td></tr>
<tr class="separator:gae2e70de7b1bc13041c7e649c37c9d153"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO update - NCO update mode</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to Select event source, delay and reset delay.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gad74ad2d78a0026ecf5108d6dce965985"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad74ad2d78a0026ecf5108d6dce965985">XRFDC_NCO_UPDT_MODE_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gad74ad2d78a0026ecf5108d6dce965985"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection mask.  <a href="group___overview.html#gad74ad2d78a0026ecf5108d6dce965985">More...</a><br/></td></tr>
<tr class="separator:gad74ad2d78a0026ecf5108d6dce965985"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98d8ea06225e2e15fa4052fc9b02e770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga98d8ea06225e2e15fa4052fc9b02e770">XRFDC_NCO_UPDT_MODE_GRP</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga98d8ea06225e2e15fa4052fc9b02e770"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is Group.  <a href="group___overview.html#ga98d8ea06225e2e15fa4052fc9b02e770">More...</a><br/></td></tr>
<tr class="separator:ga98d8ea06225e2e15fa4052fc9b02e770"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55a678591c3475e6644013bab8de1d9c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga55a678591c3475e6644013bab8de1d9c">XRFDC_NCO_UPDT_MODE_SLICE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga55a678591c3475e6644013bab8de1d9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is slice.  <a href="group___overview.html#ga55a678591c3475e6644013bab8de1d9c">More...</a><br/></td></tr>
<tr class="separator:ga55a678591c3475e6644013bab8de1d9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9900132b14a27edae2d9689b6bcb6fd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9900132b14a27edae2d9689b6bcb6fd7">XRFDC_NCO_UPDT_MODE_TILE</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga9900132b14a27edae2d9689b6bcb6fd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is tile.  <a href="group___overview.html#ga9900132b14a27edae2d9689b6bcb6fd7">More...</a><br/></td></tr>
<tr class="separator:ga9900132b14a27edae2d9689b6bcb6fd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2890a0d6d3b4af6c52db6df75a969de0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2890a0d6d3b4af6c52db6df75a969de0">XRFDC_NCO_UPDT_MODE_SYSREF</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga2890a0d6d3b4af6c52db6df75a969de0"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is Sysref.  <a href="group___overview.html#ga2890a0d6d3b4af6c52db6df75a969de0">More...</a><br/></td></tr>
<tr class="separator:ga2890a0d6d3b4af6c52db6df75a969de0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac64287ad0fa6cb5f145cfd31b921a6f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac64287ad0fa6cb5f145cfd31b921a6f1">XRFDC_NCO_UPDT_MODE_MARKER</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gac64287ad0fa6cb5f145cfd31b921a6f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is Marker.  <a href="group___overview.html#gac64287ad0fa6cb5f145cfd31b921a6f1">More...</a><br/></td></tr>
<tr class="separator:gac64287ad0fa6cb5f145cfd31b921a6f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga42b76ddfd68b556e19191184968edc64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga42b76ddfd68b556e19191184968edc64">XRFDC_NCO_UPDT_MODE_FABRIC</a>&#160;&#160;&#160;0x00000005U</td></tr>
<tr class="memdesc:ga42b76ddfd68b556e19191184968edc64"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO event source selection is fabric.  <a href="group___overview.html#ga42b76ddfd68b556e19191184968edc64">More...</a><br/></td></tr>
<tr class="separator:ga42b76ddfd68b556e19191184968edc64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e6643d84a299afbce2e378bcc30b02d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e6643d84a299afbce2e378bcc30b02d">XRFDC_NCO_UPDT_DLY_MASK</a>&#160;&#160;&#160;0x00001FF8U</td></tr>
<tr class="memdesc:ga7e6643d84a299afbce2e378bcc30b02d"><td class="mdescLeft">&#160;</td><td class="mdescRight">delay in clk_dp cycles in application of event after arrival  <a href="group___overview.html#ga7e6643d84a299afbce2e378bcc30b02d">More...</a><br/></td></tr>
<tr class="separator:ga7e6643d84a299afbce2e378bcc30b02d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d2b06dceaf2ce19923b93d516cae937"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5d2b06dceaf2ce19923b93d516cae937">XRFDC_NCO_UPDT_RST_DLY_MASK</a>&#160;&#160;&#160;0x0000D000U</td></tr>
<tr class="memdesc:ga5d2b06dceaf2ce19923b93d516cae937"><td class="mdescLeft">&#160;</td><td class="mdescRight">optional delay on the NCO phase reset delay  <a href="group___overview.html#ga5d2b06dceaf2ce19923b93d516cae937">More...</a><br/></td></tr>
<tr class="separator:ga5d2b06dceaf2ce19923b93d516cae937"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Phase Reset - NCO Slice Phase Reset</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to reset the nco phase of the current slice phase accumulator.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga65c3d6803aaf91bc403614b78fd8742f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga65c3d6803aaf91bc403614b78fd8742f">XRFDC_NCO_PHASE_RST_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga65c3d6803aaf91bc403614b78fd8742f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset NCO Phase of current slice.  <a href="group___overview.html#ga65c3d6803aaf91bc403614b78fd8742f">More...</a><br/></td></tr>
<tr class="separator:ga65c3d6803aaf91bc403614b78fd8742f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DAC interpolation data</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for DAC interpolation data type </p>
</div></td></tr>
<tr class="memitem:ga3c759fe5c55126808f5d02e6d66fd1fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3c759fe5c55126808f5d02e6d66fd1fe">XRFDC_DAC_INTERP_DATA_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga3c759fe5c55126808f5d02e6d66fd1fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data type mask.  <a href="group___overview.html#ga3c759fe5c55126808f5d02e6d66fd1fe">More...</a><br/></td></tr>
<tr class="separator:ga3c759fe5c55126808f5d02e6d66fd1fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for frequency control word of the NCO.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gafc580daf242966b54276a73925eb9f41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafc580daf242966b54276a73925eb9f41">XRFDC_NCO_FQWD_UPP_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gafc580daf242966b54276a73925eb9f41"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase increment[47:32].  <a href="group___overview.html#gafc580daf242966b54276a73925eb9f41">More...</a><br/></td></tr>
<tr class="separator:gafc580daf242966b54276a73925eb9f41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cf794621d971e07a4965492adfb5116"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6cf794621d971e07a4965492adfb5116">XRFDC_NCO_FQWD_UPP_SHIFT</a>&#160;&#160;&#160;32U</td></tr>
<tr class="memdesc:ga6cf794621d971e07a4965492adfb5116"><td class="mdescLeft">&#160;</td><td class="mdescRight">Freq Word upper shift.  <a href="group___overview.html#ga6cf794621d971e07a4965492adfb5116">More...</a><br/></td></tr>
<tr class="separator:ga6cf794621d971e07a4965492adfb5116"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for frequency control word of the NCO.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga837c6d61b88a53aee708e95491eeb8fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga837c6d61b88a53aee708e95491eeb8fe">XRFDC_NCO_FQWD_MID_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga837c6d61b88a53aee708e95491eeb8fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase increment[31:16].  <a href="group___overview.html#ga837c6d61b88a53aee708e95491eeb8fe">More...</a><br/></td></tr>
<tr class="separator:ga837c6d61b88a53aee708e95491eeb8fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc041f02657febd798b944b98f982e6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacc041f02657febd798b944b98f982e6c">XRFDC_NCO_FQWD_MID_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:gacc041f02657febd798b944b98f982e6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Freq Word Mid shift.  <a href="group___overview.html#gacc041f02657febd798b944b98f982e6c">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for frequency control word of the NCO.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga8209772bd4995cf6a82be46cc9e2830b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8209772bd4995cf6a82be46cc9e2830b">XRFDC_NCO_FQWD_LOW_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga8209772bd4995cf6a82be46cc9e2830b"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase increment[15:0].  <a href="group___overview.html#ga8209772bd4995cf6a82be46cc9e2830b">More...</a><br/></td></tr>
<tr class="separator:ga8209772bd4995cf6a82be46cc9e2830b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83d738e52ab11916329617478f96876d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga83d738e52ab11916329617478f96876d">XRFDC_NCO_FQWD_MASK</a>&#160;&#160;&#160;0x0000FFFFFFFFFFFFU</td></tr>
<tr class="memdesc:ga83d738e52ab11916329617478f96876d"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Freq offset[48:0].  <a href="group___overview.html#ga83d738e52ab11916329617478f96876d">More...</a><br/></td></tr>
<tr class="separator:ga83d738e52ab11916329617478f96876d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Phase Offset[17:16] - NCO Phase offset</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga511eb14fc9d93eb331304c1bb6f2fb8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga511eb14fc9d93eb331304c1bb6f2fb8f">XRFDC_NCO_PHASE_UPP_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga511eb14fc9d93eb331304c1bb6f2fb8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase offset[17:16].  <a href="group___overview.html#ga511eb14fc9d93eb331304c1bb6f2fb8f">More...</a><br/></td></tr>
<tr class="separator:ga511eb14fc9d93eb331304c1bb6f2fb8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82d1176a1527f504d142a46d13933714"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga82d1176a1527f504d142a46d13933714">XRFDC_NCO_PHASE_UPP_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga82d1176a1527f504d142a46d13933714"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO phase upper shift.  <a href="group___overview.html#ga82d1176a1527f504d142a46d13933714">More...</a><br/></td></tr>
<tr class="separator:ga82d1176a1527f504d142a46d13933714"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Phase Offset[15:0] - NCO Phase offset</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga91eaf8035d77f447fc850dac646a70d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga91eaf8035d77f447fc850dac646a70d6">XRFDC_NCO_PHASE_LOW_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga91eaf8035d77f447fc850dac646a70d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase offset[15:0].  <a href="group___overview.html#ga91eaf8035d77f447fc850dac646a70d6">More...</a><br/></td></tr>
<tr class="separator:ga91eaf8035d77f447fc850dac646a70d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae836b18a6c12fa69635005be31b80647"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae836b18a6c12fa69635005be31b80647">XRFDC_NCO_PHASE_MASK</a>&#160;&#160;&#160;0x0003FFFFU</td></tr>
<tr class="memdesc:gae836b18a6c12fa69635005be31b80647"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO Phase offset[17:0].  <a href="group___overview.html#gae836b18a6c12fa69635005be31b80647">More...</a><br/></td></tr>
<tr class="separator:gae836b18a6c12fa69635005be31b80647"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">NCO Phase mode - NCO Control setting mode</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set NCO mode of operation.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gac08a562c8f68737ccb5d89576d144ab5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac08a562c8f68737ccb5d89576d144ab5">XRFDC_NCO_PHASE_MOD_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gac08a562c8f68737ccb5d89576d144ab5"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO mode of operation mask.  <a href="group___overview.html#gac08a562c8f68737ccb5d89576d144ab5">More...</a><br/></td></tr>
<tr class="separator:gac08a562c8f68737ccb5d89576d144ab5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbf0034981ebc0ed6110175178578234"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacbf0034981ebc0ed6110175178578234">XRFDC_NCO_PHASE_MOD_4PHASE</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gacbf0034981ebc0ed6110175178578234"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO output 4 successive phase.  <a href="group___overview.html#gacbf0034981ebc0ed6110175178578234">More...</a><br/></td></tr>
<tr class="separator:gacbf0034981ebc0ed6110175178578234"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab67ff65090cbb823086d18c220c0b1e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab67ff65090cbb823086d18c220c0b1e4">XRFDC_NCO_PHASE_MOD_EVEN</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gab67ff65090cbb823086d18c220c0b1e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO output even phase.  <a href="group___overview.html#gab67ff65090cbb823086d18c220c0b1e4">More...</a><br/></td></tr>
<tr class="separator:gab67ff65090cbb823086d18c220c0b1e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94aae7714e373d3484d9a44a9accdd21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga94aae7714e373d3484d9a44a9accdd21">XRFDC_NCO_PHASE_MODE_ODD</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga94aae7714e373d3484d9a44a9accdd21"><td class="mdescLeft">&#160;</td><td class="mdescRight">NCO output odd phase.  <a href="group___overview.html#ga94aae7714e373d3484d9a44a9accdd21">More...</a><br/></td></tr>
<tr class="separator:ga94aae7714e373d3484d9a44a9accdd21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QMC update - QMC update mode</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to Select event source and delay.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gac5bfb9bb3f007c86cf52e2d935d9b0f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac5bfb9bb3f007c86cf52e2d935d9b0f9">XRFDC_QMC_UPDT_MODE_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gac5bfb9bb3f007c86cf52e2d935d9b0f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection mask.  <a href="group___overview.html#gac5bfb9bb3f007c86cf52e2d935d9b0f9">More...</a><br/></td></tr>
<tr class="separator:gac5bfb9bb3f007c86cf52e2d935d9b0f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40f9a0ec45792b9fd087c42b15d680cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga40f9a0ec45792b9fd087c42b15d680cf">XRFDC_QMC_UPDT_MODE_GRP</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga40f9a0ec45792b9fd087c42b15d680cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is group.  <a href="group___overview.html#ga40f9a0ec45792b9fd087c42b15d680cf">More...</a><br/></td></tr>
<tr class="separator:ga40f9a0ec45792b9fd087c42b15d680cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e174f0794efddc89198edd71375cc20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e174f0794efddc89198edd71375cc20">XRFDC_QMC_UPDT_MODE_SLICE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga7e174f0794efddc89198edd71375cc20"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is slice.  <a href="group___overview.html#ga7e174f0794efddc89198edd71375cc20">More...</a><br/></td></tr>
<tr class="separator:ga7e174f0794efddc89198edd71375cc20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4c28277d76d7a273fe23b4aa56886e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad4c28277d76d7a273fe23b4aa56886e1">XRFDC_QMC_UPDT_MODE_TILE</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gad4c28277d76d7a273fe23b4aa56886e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is tile.  <a href="group___overview.html#gad4c28277d76d7a273fe23b4aa56886e1">More...</a><br/></td></tr>
<tr class="separator:gad4c28277d76d7a273fe23b4aa56886e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45441dca57609804914d6aefbd281563"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga45441dca57609804914d6aefbd281563">XRFDC_QMC_UPDT_MODE_SYSREF</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga45441dca57609804914d6aefbd281563"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is Sysref.  <a href="group___overview.html#ga45441dca57609804914d6aefbd281563">More...</a><br/></td></tr>
<tr class="separator:ga45441dca57609804914d6aefbd281563"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94660f0b0c3aa2c5a0eae59bd55bbc75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga94660f0b0c3aa2c5a0eae59bd55bbc75">XRFDC_QMC_UPDT_MODE_MARKER</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga94660f0b0c3aa2c5a0eae59bd55bbc75"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is Marker.  <a href="group___overview.html#ga94660f0b0c3aa2c5a0eae59bd55bbc75">More...</a><br/></td></tr>
<tr class="separator:ga94660f0b0c3aa2c5a0eae59bd55bbc75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4acd23abf7d3e5ad1e8d57583835293e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4acd23abf7d3e5ad1e8d57583835293e">XRFDC_QMC_UPDT_MODE_FABRIC</a>&#160;&#160;&#160;0x00000005U</td></tr>
<tr class="memdesc:ga4acd23abf7d3e5ad1e8d57583835293e"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC event source selection is fabric.  <a href="group___overview.html#ga4acd23abf7d3e5ad1e8d57583835293e">More...</a><br/></td></tr>
<tr class="separator:ga4acd23abf7d3e5ad1e8d57583835293e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0e7f511db29c6b6b6298cea7706d3cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa0e7f511db29c6b6b6298cea7706d3cd">XRFDC_QMC_UPDT_DLY_MASK</a>&#160;&#160;&#160;0x00001FF8U</td></tr>
<tr class="memdesc:gaa0e7f511db29c6b6b6298cea7706d3cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">delay in clk_dp cycles in application of event after arrival  <a href="group___overview.html#gaa0e7f511db29c6b6b6298cea7706d3cd">More...</a><br/></td></tr>
<tr class="separator:gaa0e7f511db29c6b6b6298cea7706d3cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QMC Config - QMC Config register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to enable QMC gain and QMC Phase correction.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gabe7004e6cf9b489e33a91d6c260c2668"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabe7004e6cf9b489e33a91d6c260c2668">XRFDC_QMC_CFG_EN_GAIN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gabe7004e6cf9b489e33a91d6c260c2668"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable QMC gain correction mask  <a href="group___overview.html#gabe7004e6cf9b489e33a91d6c260c2668">More...</a><br/></td></tr>
<tr class="separator:gabe7004e6cf9b489e33a91d6c260c2668"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga594d5be058e8d9d0c8c66dbd61096c0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga594d5be058e8d9d0c8c66dbd61096c0c">XRFDC_QMC_CFG_EN_PHASE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga594d5be058e8d9d0c8c66dbd61096c0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable QMC Phase correction mask  <a href="group___overview.html#ga594d5be058e8d9d0c8c66dbd61096c0c">More...</a><br/></td></tr>
<tr class="separator:ga594d5be058e8d9d0c8c66dbd61096c0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c5eb86950c6cc5a41f9a18d22d199d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7c5eb86950c6cc5a41f9a18d22d199d5">XRFDC_QMC_CFG_PHASE_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga7c5eb86950c6cc5a41f9a18d22d199d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC config phase shift.  <a href="group___overview.html#ga7c5eb86950c6cc5a41f9a18d22d199d5">More...</a><br/></td></tr>
<tr class="separator:ga7c5eb86950c6cc5a41f9a18d22d199d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QMC Offset - QMC offset correction</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set QMC offset correction factor.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga071793b0bb699ee99defa1954b7a6d00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga071793b0bb699ee99defa1954b7a6d00">XRFDC_QMC_OFFST_CRCTN_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:ga071793b0bb699ee99defa1954b7a6d00"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC offset correction factor.  <a href="group___overview.html#ga071793b0bb699ee99defa1954b7a6d00">More...</a><br/></td></tr>
<tr class="separator:ga071793b0bb699ee99defa1954b7a6d00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32a855184917be523a8117c513606d6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga32a855184917be523a8117c513606d6d">XRFDC_QMC_OFFST_CRCTN_SIGN_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga32a855184917be523a8117c513606d6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC offset correction factor sign bit.  <a href="group___overview.html#ga32a855184917be523a8117c513606d6d">More...</a><br/></td></tr>
<tr class="separator:ga32a855184917be523a8117c513606d6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QMC Gain - QMC Gain correction</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set QMC gain correction factor.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga3c4647593fad2b0af4b0aeb4f79b3561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3c4647593fad2b0af4b0aeb4f79b3561">XRFDC_QMC_GAIN_CRCTN_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:ga3c4647593fad2b0af4b0aeb4f79b3561"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC gain correction factor.  <a href="group___overview.html#ga3c4647593fad2b0af4b0aeb4f79b3561">More...</a><br/></td></tr>
<tr class="separator:ga3c4647593fad2b0af4b0aeb4f79b3561"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QMC Phase - QMC Phase correction</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to set QMC phase correction factor.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga1f180b34a8de21344c0a903dcfa23c7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1f180b34a8de21344c0a903dcfa23c7d">XRFDC_QMC_PHASE_CRCTN_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:ga1f180b34a8de21344c0a903dcfa23c7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC phase correction factor.  <a href="group___overview.html#ga1f180b34a8de21344c0a903dcfa23c7d">More...</a><br/></td></tr>
<tr class="separator:ga1f180b34a8de21344c0a903dcfa23c7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3074028b200520a1481c97be1f23e730"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3074028b200520a1481c97be1f23e730">XRFDC_QMC_PHASE_CRCTN_SIGN_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga3074028b200520a1481c97be1f23e730"><td class="mdescLeft">&#160;</td><td class="mdescRight">QMC phase correction factor sign bit.  <a href="group___overview.html#ga3074028b200520a1481c97be1f23e730">More...</a><br/></td></tr>
<tr class="separator:ga3074028b200520a1481c97be1f23e730"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Coarse Delay Update - Coarse delay update mode.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to Select event source and delay.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga30eb14bf2f6e7df6bca5ea95eff3f57b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga30eb14bf2f6e7df6bca5ea95eff3f57b">XRFDC_CRSEDLY_UPDT_MODE_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga30eb14bf2f6e7df6bca5ea95eff3f57b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection mask.  <a href="group___overview.html#ga30eb14bf2f6e7df6bca5ea95eff3f57b">More...</a><br/></td></tr>
<tr class="separator:ga30eb14bf2f6e7df6bca5ea95eff3f57b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeed9a17cf318f8bf209b4779a8a1370"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadeed9a17cf318f8bf209b4779a8a1370">XRFDC_CRSEDLY_UPDT_MODE_GRP</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gadeed9a17cf318f8bf209b4779a8a1370"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is group.  <a href="group___overview.html#gadeed9a17cf318f8bf209b4779a8a1370">More...</a><br/></td></tr>
<tr class="separator:gadeed9a17cf318f8bf209b4779a8a1370"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15476d65ea5280dca690d4eeb754b413"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga15476d65ea5280dca690d4eeb754b413">XRFDC_CRSEDLY_UPDT_MODE_SLICE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga15476d65ea5280dca690d4eeb754b413"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is slice.  <a href="group___overview.html#ga15476d65ea5280dca690d4eeb754b413">More...</a><br/></td></tr>
<tr class="separator:ga15476d65ea5280dca690d4eeb754b413"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6869e004b973c280fbfb5fac7047b9e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6869e004b973c280fbfb5fac7047b9e3">XRFDC_CRSEDLY_UPDT_MODE_TILE</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga6869e004b973c280fbfb5fac7047b9e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is tile.  <a href="group___overview.html#ga6869e004b973c280fbfb5fac7047b9e3">More...</a><br/></td></tr>
<tr class="separator:ga6869e004b973c280fbfb5fac7047b9e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2171529912a2e514910ad80d6ea42f32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2171529912a2e514910ad80d6ea42f32">XRFDC_CRSEDLY_UPDT_MODE_SYSREF</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga2171529912a2e514910ad80d6ea42f32"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is sysref.  <a href="group___overview.html#ga2171529912a2e514910ad80d6ea42f32">More...</a><br/></td></tr>
<tr class="separator:ga2171529912a2e514910ad80d6ea42f32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65ed15a5ee6c55a5dfbe8b744aebfd52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga65ed15a5ee6c55a5dfbe8b744aebfd52">XRFDC_CRSEDLY_UPDT_MODE_MARKER</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga65ed15a5ee6c55a5dfbe8b744aebfd52"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is Marker.  <a href="group___overview.html#ga65ed15a5ee6c55a5dfbe8b744aebfd52">More...</a><br/></td></tr>
<tr class="separator:ga65ed15a5ee6c55a5dfbe8b744aebfd52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga969c48a40fa8601f89b2cd7db85cd9e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga969c48a40fa8601f89b2cd7db85cd9e7">XRFDC_CRSEDLY_UPDT_MODE_FABRIC</a>&#160;&#160;&#160;0x00000005U</td></tr>
<tr class="memdesc:ga969c48a40fa8601f89b2cd7db85cd9e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay event source selection is fabric.  <a href="group___overview.html#ga969c48a40fa8601f89b2cd7db85cd9e7">More...</a><br/></td></tr>
<tr class="separator:ga969c48a40fa8601f89b2cd7db85cd9e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f26a7fa419fea64aef82c154964bc8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7f26a7fa419fea64aef82c154964bc8f">XRFDC_CRSEDLY_UPDT_DLY_MASK</a>&#160;&#160;&#160;0x00001FF8U</td></tr>
<tr class="memdesc:ga7f26a7fa419fea64aef82c154964bc8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">delay in clk_dp cycles in application of event after arrival  <a href="group___overview.html#ga7f26a7fa419fea64aef82c154964bc8f">More...</a><br/></td></tr>
<tr class="separator:ga7f26a7fa419fea64aef82c154964bc8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Coarse delay Config - Coarse delay select</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select coarse delay.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaeac24dc718cb4a01d6471e7f18491e3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaeac24dc718cb4a01d6471e7f18491e3c">XRFDC_CRSE_DLY_CFG_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gaeac24dc718cb4a01d6471e7f18491e3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coarse delay select.  <a href="group___overview.html#gaeac24dc718cb4a01d6471e7f18491e3c">More...</a><br/></td></tr>
<tr class="separator:gaeac24dc718cb4a01d6471e7f18491e3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7858e858395377fe3f269964d644f711"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7858e858395377fe3f269964d644f711">XRFDC_CRSE_DLY_CFG_MASK_EXT</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga7858e858395377fe3f269964d644f711"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended coarse delay select.  <a href="group___overview.html#ga7858e858395377fe3f269964d644f711">More...</a><br/></td></tr>
<tr class="separator:ga7858e858395377fe3f269964d644f711"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Scaling Config - Data Scaling enable</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to enable data scaling.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga952f94581d63d8a8ef8394419a4e2950"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga952f94581d63d8a8ef8394419a4e2950">XRFDC_DAT_SCALE_CFG_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga952f94581d63d8a8ef8394419a4e2950"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable data scaling.  <a href="group___overview.html#ga952f94581d63d8a8ef8394419a4e2950">More...</a><br/></td></tr>
<tr class="separator:ga952f94581d63d8a8ef8394419a4e2950"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga952f94581d63d8a8ef8394419a4e2950"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga952f94581d63d8a8ef8394419a4e2950">XRFDC_DAT_SCALE_CFG_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga952f94581d63d8a8ef8394419a4e2950"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable data scaling.  <a href="group___overview.html#ga952f94581d63d8a8ef8394419a4e2950">More...</a><br/></td></tr>
<tr class="separator:ga952f94581d63d8a8ef8394419a4e2950"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Switch Matrix Config</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to control crossbar switch that select data to mixer block.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga65ab7f10e67b3eab887dce8198cc8806"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga65ab7f10e67b3eab887dce8198cc8806">XRFDC_SWITCH_MTRX_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga65ab7f10e67b3eab887dce8198cc8806"><td class="mdescLeft">&#160;</td><td class="mdescRight">Switch matrix mask.  <a href="group___overview.html#ga65ab7f10e67b3eab887dce8198cc8806">More...</a><br/></td></tr>
<tr class="separator:ga65ab7f10e67b3eab887dce8198cc8806"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5cf885da2bb4a064d97cbb8584d4e7ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5cf885da2bb4a064d97cbb8584d4e7ee">XRFDC_SEL_CB_TO_MIX1_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga5cf885da2bb4a064d97cbb8584d4e7ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control crossbar switch that select the data to mixer block mux1.  <a href="group___overview.html#ga5cf885da2bb4a064d97cbb8584d4e7ee">More...</a><br/></td></tr>
<tr class="separator:ga5cf885da2bb4a064d97cbb8584d4e7ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66e3ff3790dcdc377d7c3d006839d9c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga66e3ff3790dcdc377d7c3d006839d9c7">XRFDC_SEL_CB_TO_MIX0_MASK</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:ga66e3ff3790dcdc377d7c3d006839d9c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control crossbar switch that select the data to mixer block mux0.  <a href="group___overview.html#ga66e3ff3790dcdc377d7c3d006839d9c7">More...</a><br/></td></tr>
<tr class="separator:ga66e3ff3790dcdc377d7c3d006839d9c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8d738ffbe6e827dc9359fad5fdab79a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac8d738ffbe6e827dc9359fad5fdab79a">XRFDC_SEL_CB_TO_QMC_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gac8d738ffbe6e827dc9359fad5fdab79a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control crossbar switch that select the data to QMC.  <a href="group___overview.html#gac8d738ffbe6e827dc9359fad5fdab79a">More...</a><br/></td></tr>
<tr class="separator:gac8d738ffbe6e827dc9359fad5fdab79a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee3d96f330a569976d1c77a967c1f185"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaee3d96f330a569976d1c77a967c1f185">XRFDC_SEL_CB_TO_DECI_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaee3d96f330a569976d1c77a967c1f185"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control crossbar switch that select the data to decimation filter.  <a href="group___overview.html#gaee3d96f330a569976d1c77a967c1f185">More...</a><br/></td></tr>
<tr class="separator:gaee3d96f330a569976d1c77a967c1f185"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf8f9dad4b6c97472a5ba429592c67d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadf8f9dad4b6c97472a5ba429592c67d1">XRFDC_SEL_CB_TO_MIX0_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gadf8f9dad4b6c97472a5ba429592c67d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Crossbar Mixer0 shift.  <a href="group___overview.html#gadf8f9dad4b6c97472a5ba429592c67d1">More...</a><br/></td></tr>
<tr class="separator:gadf8f9dad4b6c97472a5ba429592c67d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold0 Config</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select mode, clear mode and to clear sticky bit.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga2c4631be6cebecd9af303c3f6bd8c338"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2c4631be6cebecd9af303c3f6bd8c338">XRFDC_TRSHD0_EN_MOD_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga2c4631be6cebecd9af303c3f6bd8c338"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Threshold0 block.  <a href="group___overview.html#ga2c4631be6cebecd9af303c3f6bd8c338">More...</a><br/></td></tr>
<tr class="separator:ga2c4631be6cebecd9af303c3f6bd8c338"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02af84ef0928e09e3ed9d9f2639409c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga02af84ef0928e09e3ed9d9f2639409c8">XRFDC_TRSHD0_CLR_MOD_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga02af84ef0928e09e3ed9d9f2639409c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear mode.  <a href="group___overview.html#ga02af84ef0928e09e3ed9d9f2639409c8">More...</a><br/></td></tr>
<tr class="separator:ga02af84ef0928e09e3ed9d9f2639409c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d14cc79a3a529a1d2de6a1c9f8061e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0d14cc79a3a529a1d2de6a1c9f8061e4">XRFDC_TRSHD0_STIKY_CLR_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga0d14cc79a3a529a1d2de6a1c9f8061e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear sticky bit.  <a href="group___overview.html#ga0d14cc79a3a529a1d2de6a1c9f8061e4">More...</a><br/></td></tr>
<tr class="separator:ga0d14cc79a3a529a1d2de6a1c9f8061e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold0 Average[31:16]</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold0 under averaging.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gab3ecc88b27a7ee0b7ca37007c3e761e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab3ecc88b27a7ee0b7ca37007c3e761e7">XRFDC_TRSHD0_AVG_UPP_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gab3ecc88b27a7ee0b7ca37007c3e761e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold0 under Averaging[31:16].  <a href="group___overview.html#gab3ecc88b27a7ee0b7ca37007c3e761e7">More...</a><br/></td></tr>
<tr class="separator:gab3ecc88b27a7ee0b7ca37007c3e761e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga241937dd7399a4dab70bc7457dc58941"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga241937dd7399a4dab70bc7457dc58941">XRFDC_TRSHD0_AVG_UPP_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga241937dd7399a4dab70bc7457dc58941"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold0 Avg upper shift.  <a href="group___overview.html#ga241937dd7399a4dab70bc7457dc58941">More...</a><br/></td></tr>
<tr class="separator:ga241937dd7399a4dab70bc7457dc58941"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold0 Average[15:0]</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold0 under averaging.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga4900a9b8a5160c5c3ca37082eb9e03ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4900a9b8a5160c5c3ca37082eb9e03ba">XRFDC_TRSHD0_AVG_LOW_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga4900a9b8a5160c5c3ca37082eb9e03ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold0 under Averaging[15:0].  <a href="group___overview.html#ga4900a9b8a5160c5c3ca37082eb9e03ba">More...</a><br/></td></tr>
<tr class="separator:ga4900a9b8a5160c5c3ca37082eb9e03ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold0 Under threshold</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold0 under threshold.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gacf3bfb2c38fdd53bd2e6d016656a034a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacf3bfb2c38fdd53bd2e6d016656a034a">XRFDC_TRSHD0_UNDER_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:gacf3bfb2c38fdd53bd2e6d016656a034a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold0 under Threshold[13:0].  <a href="group___overview.html#gacf3bfb2c38fdd53bd2e6d016656a034a">More...</a><br/></td></tr>
<tr class="separator:gacf3bfb2c38fdd53bd2e6d016656a034a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold0 Over threshold</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold0 over threshold.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga1063718156e42b25517c7d0f7da69ce2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1063718156e42b25517c7d0f7da69ce2">XRFDC_TRSHD0_OVER_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:ga1063718156e42b25517c7d0f7da69ce2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold0 under Threshold[13:0].  <a href="group___overview.html#ga1063718156e42b25517c7d0f7da69ce2">More...</a><br/></td></tr>
<tr class="separator:ga1063718156e42b25517c7d0f7da69ce2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold1 Config</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select mode, clear mode and to clear sticky bit.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga25fb89e74517cfec924ea6ee1d9ed306"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga25fb89e74517cfec924ea6ee1d9ed306">XRFDC_TRSHD1_EN_MOD_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga25fb89e74517cfec924ea6ee1d9ed306"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Threshold1 block.  <a href="group___overview.html#ga25fb89e74517cfec924ea6ee1d9ed306">More...</a><br/></td></tr>
<tr class="separator:ga25fb89e74517cfec924ea6ee1d9ed306"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaff6bb032998c703e8a098e469e9074f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaaff6bb032998c703e8a098e469e9074f">XRFDC_TRSHD1_CLR_MOD_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gaaff6bb032998c703e8a098e469e9074f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear mode.  <a href="group___overview.html#gaaff6bb032998c703e8a098e469e9074f">More...</a><br/></td></tr>
<tr class="separator:gaaff6bb032998c703e8a098e469e9074f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62fbe53a9ebbeb9703ec90e92d97dbfc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga62fbe53a9ebbeb9703ec90e92d97dbfc">XRFDC_TRSHD1_STIKY_CLR_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga62fbe53a9ebbeb9703ec90e92d97dbfc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear sticky bit.  <a href="group___overview.html#ga62fbe53a9ebbeb9703ec90e92d97dbfc">More...</a><br/></td></tr>
<tr class="separator:ga62fbe53a9ebbeb9703ec90e92d97dbfc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold1 Average[31:16]</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold1 under averaging.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga413088467612fed50166cecb96be66a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga413088467612fed50166cecb96be66a7">XRFDC_TRSHD1_AVG_UPP_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga413088467612fed50166cecb96be66a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold1 under Averaging[31:16].  <a href="group___overview.html#ga413088467612fed50166cecb96be66a7">More...</a><br/></td></tr>
<tr class="separator:ga413088467612fed50166cecb96be66a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02ebba9852b1f6c40a7cf69c63e96a35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga02ebba9852b1f6c40a7cf69c63e96a35">XRFDC_TRSHD1_AVG_UPP_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga02ebba9852b1f6c40a7cf69c63e96a35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold1 Avg upper shift.  <a href="group___overview.html#ga02ebba9852b1f6c40a7cf69c63e96a35">More...</a><br/></td></tr>
<tr class="separator:ga02ebba9852b1f6c40a7cf69c63e96a35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold1 Average[15:0]</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold1 under averaging.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gadb17e7832717e6bf590ee5d0bc684cef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadb17e7832717e6bf590ee5d0bc684cef">XRFDC_TRSHD1_AVG_LOW_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gadb17e7832717e6bf590ee5d0bc684cef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold1 under Averaging[15:0].  <a href="group___overview.html#gadb17e7832717e6bf590ee5d0bc684cef">More...</a><br/></td></tr>
<tr class="separator:gadb17e7832717e6bf590ee5d0bc684cef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold1 Under threshold</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold1 under threshold.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga4874aa2b9526717f14e9d993c67444d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4874aa2b9526717f14e9d993c67444d4">XRFDC_TRSHD1_UNDER_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:ga4874aa2b9526717f14e9d993c67444d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold1 under Threshold[13:0].  <a href="group___overview.html#ga4874aa2b9526717f14e9d993c67444d4">More...</a><br/></td></tr>
<tr class="separator:ga4874aa2b9526717f14e9d993c67444d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Threshold1 Over threshold</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select Threshold1 over threshold.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga7cbdbadacec444d7a2bd6d8b1ac2859c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7cbdbadacec444d7a2bd6d8b1ac2859c">XRFDC_TRSHD1_OVER_MASK</a>&#160;&#160;&#160;0x00003FFFU</td></tr>
<tr class="memdesc:ga7cbdbadacec444d7a2bd6d8b1ac2859c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Threshold1 under Threshold[13:0].  <a href="group___overview.html#ga7cbdbadacec444d7a2bd6d8b1ac2859c">More...</a><br/></td></tr>
<tr class="separator:ga7cbdbadacec444d7a2bd6d8b1ac2859c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TDD Control</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to manage the TDD Control </p>
</div></td></tr>
<tr class="memitem:gac138c45a93705e2822ae2c22cfacde85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac138c45a93705e2822ae2c22cfacde85">XRFDC_TDD_CTRL_MASK</a>&#160;&#160;&#160;0x0000001FU</td></tr>
<tr class="memdesc:gac138c45a93705e2822ae2c22cfacde85"><td class="mdescLeft">&#160;</td><td class="mdescRight">All TDD control bits.  <a href="group___overview.html#gac138c45a93705e2822ae2c22cfacde85">More...</a><br/></td></tr>
<tr class="separator:gac138c45a93705e2822ae2c22cfacde85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22c3352ee513691f82a81182e0bd738b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga22c3352ee513691f82a81182e0bd738b">XRFDC_TDD_CTRL_MODE01_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga22c3352ee513691f82a81182e0bd738b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TDD mode control bits.  <a href="group___overview.html#ga22c3352ee513691f82a81182e0bd738b">More...</a><br/></td></tr>
<tr class="separator:ga22c3352ee513691f82a81182e0bd738b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d6c985aa52bf42ab915533c2027afe1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5d6c985aa52bf42ab915533c2027afe1">XRFDC_TDD_CTRL_MODE0_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga5d6c985aa52bf42ab915533c2027afe1"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TDD control bit for Mode 0 config.  <a href="group___overview.html#ga5d6c985aa52bf42ab915533c2027afe1">More...</a><br/></td></tr>
<tr class="separator:ga5d6c985aa52bf42ab915533c2027afe1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8354c96a6efb8742be112cec04334fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab8354c96a6efb8742be112cec04334fd">XRFDC_TDD_CTRL_MODE1_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gab8354c96a6efb8742be112cec04334fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TDD control bit for Mode 1 config (unused)  <a href="group___overview.html#gab8354c96a6efb8742be112cec04334fd">More...</a><br/></td></tr>
<tr class="separator:gab8354c96a6efb8742be112cec04334fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2b0cb61a5ba135e95ab4993ed900e53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad2b0cb61a5ba135e95ab4993ed900e53">XRFDC_TDD_CTRL_OBS_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gad2b0cb61a5ba135e95ab4993ed900e53"><td class="mdescLeft">&#160;</td><td class="mdescRight">The observation port enable.  <a href="group___overview.html#gad2b0cb61a5ba135e95ab4993ed900e53">More...</a><br/></td></tr>
<tr class="separator:gad2b0cb61a5ba135e95ab4993ed900e53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5b346dc49876425f779d86f529f07b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae5b346dc49876425f779d86f529f07b9">XRFDC_TDD_CTRL_RTP_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gae5b346dc49876425f779d86f529f07b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IP RTS disable bit.  <a href="group___overview.html#gae5b346dc49876425f779d86f529f07b9">More...</a><br/></td></tr>
<tr class="separator:gae5b346dc49876425f779d86f529f07b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4297a8c236fa5aed533823102ccb2c01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4297a8c236fa5aed533823102ccb2c01">XRFDC_TDD_CTRL_RTP_OBS_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga4297a8c236fa5aed533823102ccb2c01"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IP RTS disable bit for the observation channel.  <a href="group___overview.html#ga4297a8c236fa5aed533823102ccb2c01">More...</a><br/></td></tr>
<tr class="separator:ga4297a8c236fa5aed533823102ccb2c01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16d35b86968b65656ff33363991d903c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga16d35b86968b65656ff33363991d903c">XRFDC_TDD_CTRL_MODE1_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga16d35b86968b65656ff33363991d903c"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TDD control bit for Mode 1 config (unused)  <a href="group___overview.html#ga16d35b86968b65656ff33363991d903c">More...</a><br/></td></tr>
<tr class="separator:ga16d35b86968b65656ff33363991d903c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3333d38f535b3df5cf4ac530777cf99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf3333d38f535b3df5cf4ac530777cf99">XRFDC_TDD_CTRL_OBS_EN_SHIFT</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:gaf3333d38f535b3df5cf4ac530777cf99"><td class="mdescLeft">&#160;</td><td class="mdescRight">The observation port enable.  <a href="group___overview.html#gaf3333d38f535b3df5cf4ac530777cf99">More...</a><br/></td></tr>
<tr class="separator:gaf3333d38f535b3df5cf4ac530777cf99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9443f0b18e8907df65b591461aef95dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9443f0b18e8907df65b591461aef95dc">XRFDC_TDD_CTRL_RTP_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:ga9443f0b18e8907df65b591461aef95dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IP RTS disable bit.  <a href="group___overview.html#ga9443f0b18e8907df65b591461aef95dc">More...</a><br/></td></tr>
<tr class="separator:ga9443f0b18e8907df65b591461aef95dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6419f2233943a03047c9a5b77f369d1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6419f2233943a03047c9a5b77f369d1f">XRFDC_TDD_CTRL_RTP_OBS_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:ga6419f2233943a03047c9a5b77f369d1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">The IP RTS disable bit for the observation channel.  <a href="group___overview.html#ga6419f2233943a03047c9a5b77f369d1f">More...</a><br/></td></tr>
<tr class="separator:ga6419f2233943a03047c9a5b77f369d1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FrontEnd Data Control</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to select raw data and cal coefficient to be streamed to memory.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga259ecedf1030c018d39aef3235c053a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga259ecedf1030c018d39aef3235c053a5">XRFDC_FEND_DAT_CTRL_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga259ecedf1030c018d39aef3235c053a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">raw data and cal coefficient to be streamed to memory  <a href="group___overview.html#ga259ecedf1030c018d39aef3235c053a5">More...</a><br/></td></tr>
<tr class="separator:ga259ecedf1030c018d39aef3235c053a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Digital Correction Block control0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time Interleaved digital correction block gain and offset correction.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gac073efa8b4739003f0910c5546cf7305"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac073efa8b4739003f0910c5546cf7305">XRFDC_TI_DCB_CTRL0_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gac073efa8b4739003f0910c5546cf7305"><td class="mdescLeft">&#160;</td><td class="mdescRight">TI DCB gain and offset correction.  <a href="group___overview.html#gac073efa8b4739003f0910c5546cf7305">More...</a><br/></td></tr>
<tr class="separator:gac073efa8b4739003f0910c5546cf7305"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga510d6ffa4877550fb0ad7ce3f23e1a25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga510d6ffa4877550fb0ad7ce3f23e1a25">XRFDC_TI_DCB_MODE_MASK</a>&#160;&#160;&#160;0x00007800U</td></tr>
<tr class="memdesc:ga510d6ffa4877550fb0ad7ce3f23e1a25"><td class="mdescLeft">&#160;</td><td class="mdescRight">TI DCB Mode mask.  <a href="group___overview.html#ga510d6ffa4877550fb0ad7ce3f23e1a25">More...</a><br/></td></tr>
<tr class="separator:ga510d6ffa4877550fb0ad7ce3f23e1a25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Digital Correction Block control1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time Interleaved digital correction block gain and offset correction.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga8d272b772514881dac0b5e0c772dd33b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8d272b772514881dac0b5e0c772dd33b">XRFDC_TI_DCB_CTRL1_MASK</a>&#160;&#160;&#160;0x00001FFFU</td></tr>
<tr class="memdesc:ga8d272b772514881dac0b5e0c772dd33b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TI DCB gain and offset correction.  <a href="group___overview.html#ga8d272b772514881dac0b5e0c772dd33b">More...</a><br/></td></tr>
<tr class="separator:ga8d272b772514881dac0b5e0c772dd33b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Digital Correction Block control2</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time Interleaved digital correction block gain and offset correction.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gab8e9f458a1676d3a018b5506dff31df4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab8e9f458a1676d3a018b5506dff31df4">XRFDC_TI_DCB_CTRL2_MASK</a>&#160;&#160;&#160;0x00001FFFU</td></tr>
<tr class="memdesc:gab8e9f458a1676d3a018b5506dff31df4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TI DCB gain and offset correction.  <a href="group___overview.html#gab8e9f458a1676d3a018b5506dff31df4">More...</a><br/></td></tr>
<tr class="separator:gab8e9f458a1676d3a018b5506dff31df4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew control0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew correction control bits0(enables, mode, multiplier factors, debug).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga946eb312e6d84a9ed576e0e2980037d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga946eb312e6d84a9ed576e0e2980037d2">XRFDC_TI_TISK_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga946eb312e6d84a9ed576e0e2980037d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Block Enable.  <a href="group___overview.html#ga946eb312e6d84a9ed576e0e2980037d2">More...</a><br/></td></tr>
<tr class="separator:ga946eb312e6d84a9ed576e0e2980037d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8602ee795e3a38ba34a1dba58aab26cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8602ee795e3a38ba34a1dba58aab26cc">XRFDC_TI_TISK_MODE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga8602ee795e3a38ba34a1dba58aab26cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode (2G/4G)  <a href="group___overview.html#ga8602ee795e3a38ba34a1dba58aab26cc">More...</a><br/></td></tr>
<tr class="separator:ga8602ee795e3a38ba34a1dba58aab26cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f18444e5a5b7beb24c183eec21fa4a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6f18444e5a5b7beb24c183eec21fa4a1">XRFDC_TI_TISK_ZONE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga6f18444e5a5b7beb24c183eec21fa4a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies Nyquist zone.  <a href="group___overview.html#ga6f18444e5a5b7beb24c183eec21fa4a1">More...</a><br/></td></tr>
<tr class="separator:ga6f18444e5a5b7beb24c183eec21fa4a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6880e62a7e5360c4e16961da334633ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6880e62a7e5360c4e16961da334633ab">XRFDC_TI_TISK_CHOP_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga6880e62a7e5360c4e16961da334633ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable chopping mode  <a href="group___overview.html#ga6880e62a7e5360c4e16961da334633ab">More...</a><br/></td></tr>
<tr class="separator:ga6880e62a7e5360c4e16961da334633ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e7fa6da95937c2b51f3a17a4edbe6f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e7fa6da95937c2b51f3a17a4edbe6f1">XRFDC_TI_TISK_MU_CM_MASK</a>&#160;&#160;&#160;0x000000F0U</td></tr>
<tr class="memdesc:ga7e7fa6da95937c2b51f3a17a4edbe6f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant mu_cm multiplying common mode path.  <a href="group___overview.html#ga7e7fa6da95937c2b51f3a17a4edbe6f1">More...</a><br/></td></tr>
<tr class="separator:ga7e7fa6da95937c2b51f3a17a4edbe6f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51a5d19c0447099a66b0fe519fd35e5a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga51a5d19c0447099a66b0fe519fd35e5a">XRFDC_TI_TISK_MU_DF_MASK</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:ga51a5d19c0447099a66b0fe519fd35e5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant mu_df multiplying differential path.  <a href="group___overview.html#ga51a5d19c0447099a66b0fe519fd35e5a">More...</a><br/></td></tr>
<tr class="separator:ga51a5d19c0447099a66b0fe519fd35e5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga425c82907d5dad2bd8a4277d69961b06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga425c82907d5dad2bd8a4277d69961b06">XRFDC_TI_TISK_DBG_CTRL_MASK</a>&#160;&#160;&#160;0x0000F000U</td></tr>
<tr class="memdesc:ga425c82907d5dad2bd8a4277d69961b06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug control.  <a href="group___overview.html#ga425c82907d5dad2bd8a4277d69961b06">More...</a><br/></td></tr>
<tr class="separator:ga425c82907d5dad2bd8a4277d69961b06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga851a2cca9a3a4a481c435e7dcdb99574"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga851a2cca9a3a4a481c435e7dcdb99574">XRFDC_TI_TISK_DBG_UPDT_RT_MASK</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:ga851a2cca9a3a4a481c435e7dcdb99574"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug update rate.  <a href="group___overview.html#ga851a2cca9a3a4a481c435e7dcdb99574">More...</a><br/></td></tr>
<tr class="separator:ga851a2cca9a3a4a481c435e7dcdb99574"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11561db898aeddfb4d09b28481ab9489"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga11561db898aeddfb4d09b28481ab9489">XRFDC_TI_TISK_DITH_DLY_MASK</a>&#160;&#160;&#160;0x0000E000U</td></tr>
<tr class="memdesc:ga11561db898aeddfb4d09b28481ab9489"><td class="mdescLeft">&#160;</td><td class="mdescRight">Programmable delay on dither path to match data path.  <a href="group___overview.html#ga11561db898aeddfb4d09b28481ab9489">More...</a><br/></td></tr>
<tr class="separator:ga11561db898aeddfb4d09b28481ab9489"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a63ed1351521a98f82d0e2fe0d13c8d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a63ed1351521a98f82d0e2fe0d13c8d">XRFDC_TISK_ZONE_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:ga0a63ed1351521a98f82d0e2fe0d13c8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Nyquist zone shift.  <a href="group___overview.html#ga0a63ed1351521a98f82d0e2fe0d13c8d">More...</a><br/></td></tr>
<tr class="separator:ga0a63ed1351521a98f82d0e2fe0d13c8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga049214f5c698bf1267a9911a96c1cf5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga049214f5c698bf1267a9911a96c1cf5e">XRFDC_TISK_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga049214f5c698bf1267a9911a96c1cf5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Block Enable.  <a href="group___overview.html#ga049214f5c698bf1267a9911a96c1cf5e">More...</a><br/></td></tr>
<tr class="separator:ga049214f5c698bf1267a9911a96c1cf5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a01360cbe0bea0d4556e16eccbd0a5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2a01360cbe0bea0d4556e16eccbd0a5f">XRFDC_TISK_MODE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga2a01360cbe0bea0d4556e16eccbd0a5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode (2G/4G)  <a href="group___overview.html#ga2a01360cbe0bea0d4556e16eccbd0a5f">More...</a><br/></td></tr>
<tr class="separator:ga2a01360cbe0bea0d4556e16eccbd0a5f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2aa0dbadcdf5f87eb91ac2f3ad285c35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2aa0dbadcdf5f87eb91ac2f3ad285c35">XRFDC_TISK_ZONE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga2aa0dbadcdf5f87eb91ac2f3ad285c35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies Nyquist zone.  <a href="group___overview.html#ga2aa0dbadcdf5f87eb91ac2f3ad285c35">More...</a><br/></td></tr>
<tr class="separator:ga2aa0dbadcdf5f87eb91ac2f3ad285c35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d0d02d583376c345a301dc9c290e714"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9d0d02d583376c345a301dc9c290e714">XRFDC_TISK_CHOP_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9d0d02d583376c345a301dc9c290e714"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable chopping mode  <a href="group___overview.html#ga9d0d02d583376c345a301dc9c290e714">More...</a><br/></td></tr>
<tr class="separator:ga9d0d02d583376c345a301dc9c290e714"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a19a5ce21326882cfb5ef0b252bfd49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8a19a5ce21326882cfb5ef0b252bfd49">XRFDC_TISK_MU_CM_MASK</a>&#160;&#160;&#160;0x000000F0U</td></tr>
<tr class="memdesc:ga8a19a5ce21326882cfb5ef0b252bfd49"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant mu_cm multiplying common mode path.  <a href="group___overview.html#ga8a19a5ce21326882cfb5ef0b252bfd49">More...</a><br/></td></tr>
<tr class="separator:ga8a19a5ce21326882cfb5ef0b252bfd49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d6a34ef14b86ff6720805c14eb8d471"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0d6a34ef14b86ff6720805c14eb8d471">XRFDC_TISK_MU_DF_MASK</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:ga0d6a34ef14b86ff6720805c14eb8d471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant mu_df multiplying differential path.  <a href="group___overview.html#ga0d6a34ef14b86ff6720805c14eb8d471">More...</a><br/></td></tr>
<tr class="separator:ga0d6a34ef14b86ff6720805c14eb8d471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b118ea940ba32280a2d6cf9ee175f6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9b118ea940ba32280a2d6cf9ee175f6c">XRFDC_TISK_DBG_CTRL_MASK</a>&#160;&#160;&#160;0x0000F000U</td></tr>
<tr class="memdesc:ga9b118ea940ba32280a2d6cf9ee175f6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug control.  <a href="group___overview.html#ga9b118ea940ba32280a2d6cf9ee175f6c">More...</a><br/></td></tr>
<tr class="separator:ga9b118ea940ba32280a2d6cf9ee175f6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a0c7b303ee91ff885f222f545c48515"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a0c7b303ee91ff885f222f545c48515">XRFDC_TISK_DBG_UPDT_RT_MASK</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:ga9a0c7b303ee91ff885f222f545c48515"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug update rate.  <a href="group___overview.html#ga9a0c7b303ee91ff885f222f545c48515">More...</a><br/></td></tr>
<tr class="separator:ga9a0c7b303ee91ff885f222f545c48515"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9c9959175cd8dc78ccff8cbe1a60d55c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9c9959175cd8dc78ccff8cbe1a60d55c">XRFDC_TISK_DITH_DLY_MASK</a>&#160;&#160;&#160;0x0000E000U</td></tr>
<tr class="memdesc:ga9c9959175cd8dc78ccff8cbe1a60d55c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Programmable delay on dither path to match data path.  <a href="group___overview.html#ga9c9959175cd8dc78ccff8cbe1a60d55c">More...</a><br/></td></tr>
<tr class="separator:ga9c9959175cd8dc78ccff8cbe1a60d55c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DAC MC Config0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for enable/disable shadow logic , Nyquist zone selection, enable full speed clock, Programmable delay. </p>
</div></td></tr>
<tr class="memitem:ga41579834b8f26afbb9fe452c5ecb45f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga41579834b8f26afbb9fe452c5ecb45f7">XRFDC_MC_CFG0_MIX_MODE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga41579834b8f26afbb9fe452c5ecb45f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Mixing mode.  <a href="group___overview.html#ga41579834b8f26afbb9fe452c5ecb45f7">More...</a><br/></td></tr>
<tr class="separator:ga41579834b8f26afbb9fe452c5ecb45f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ad736e60ea162390707addd95791bc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8ad736e60ea162390707addd95791bc0">XRFDC_MC_CFG0_MIX_MODE_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga8ad736e60ea162390707addd95791bc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mix mode shift.  <a href="group___overview.html#ga8ad736e60ea162390707addd95791bc0">More...</a><br/></td></tr>
<tr class="separator:ga8ad736e60ea162390707addd95791bc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew control1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew correction control bits1 (Deadzone Parameters).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gad03efeb4afcbf2992ae5bee663b0a799"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad03efeb4afcbf2992ae5bee663b0a799">XRFDC_TISK_DZ_MIN_VAL_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gad03efeb4afcbf2992ae5bee663b0a799"><td class="mdescLeft">&#160;</td><td class="mdescRight">Deadzone min.  <a href="group___overview.html#gad03efeb4afcbf2992ae5bee663b0a799">More...</a><br/></td></tr>
<tr class="separator:gad03efeb4afcbf2992ae5bee663b0a799"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga46c0f163276112dca7ad77ad33ea0737"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga46c0f163276112dca7ad77ad33ea0737">XRFDC_TISK_DZ_MAX_VAL_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:ga46c0f163276112dca7ad77ad33ea0737"><td class="mdescLeft">&#160;</td><td class="mdescRight">Deadzone max.  <a href="group___overview.html#ga46c0f163276112dca7ad77ad33ea0737">More...</a><br/></td></tr>
<tr class="separator:ga46c0f163276112dca7ad77ad33ea0737"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew control2</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew correction control bits2 (Filter parameters).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gad3eaa69892000f0d3083fb90dafb6254"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad3eaa69892000f0d3083fb90dafb6254">XRFDC_TISK_MU0_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:gad3eaa69892000f0d3083fb90dafb6254"><td class="mdescLeft">&#160;</td><td class="mdescRight">Filter0 multiplying factor.  <a href="group___overview.html#gad3eaa69892000f0d3083fb90dafb6254">More...</a><br/></td></tr>
<tr class="separator:gad3eaa69892000f0d3083fb90dafb6254"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94e22d750c5bb173daef63d56da347c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga94e22d750c5bb173daef63d56da347c7">XRFDC_TISK_BYPASS0_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga94e22d750c5bb173daef63d56da347c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">ByPass filter0.  <a href="group___overview.html#ga94e22d750c5bb173daef63d56da347c7">More...</a><br/></td></tr>
<tr class="separator:ga94e22d750c5bb173daef63d56da347c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf01c753ce78e3cf2c8eea72702e76451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf01c753ce78e3cf2c8eea72702e76451">XRFDC_TISK_MU1_MASK</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:gaf01c753ce78e3cf2c8eea72702e76451"><td class="mdescLeft">&#160;</td><td class="mdescRight">Filter1 multiplying factor.  <a href="group___overview.html#gaf01c753ce78e3cf2c8eea72702e76451">More...</a><br/></td></tr>
<tr class="separator:gaf01c753ce78e3cf2c8eea72702e76451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0829e77bafb097946bab6b92e38d626a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0829e77bafb097946bab6b92e38d626a">XRFDC_TISK_BYPASS1_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga0829e77bafb097946bab6b92e38d626a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Filter1 multiplying factor.  <a href="group___overview.html#ga0829e77bafb097946bab6b92e38d626a">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew control3</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew control settling time following code update.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gabef847945f442b1cf0f3d63c0d1c33d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabef847945f442b1cf0f3d63c0d1c33d0">XRFDC_TISK_SETTLE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gabef847945f442b1cf0f3d63c0d1c33d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Settling time following code update.  <a href="group___overview.html#gabef847945f442b1cf0f3d63c0d1c33d0">More...</a><br/></td></tr>
<tr class="separator:gabef847945f442b1cf0f3d63c0d1c33d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew control4</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew control setting time following code update.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gae6dead744e5b81175ca7cb8ee3ba80d7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae6dead744e5b81175ca7cb8ee3ba80d7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_TISK_CAL_PRI_MASK</b>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="separator:gae6dead744e5b81175ca7cb8ee3ba80d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31f69ff6a3e8f0a60dd7ee253c6a1d7f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga31f69ff6a3e8f0a60dd7ee253c6a1d7f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_TISK_DITH_INV_MASK</b>&#160;&#160;&#160;0x00000FF0U</td></tr>
<tr class="separator:ga31f69ff6a3e8f0a60dd7ee253c6a1d7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew DAC0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch0.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaab914937d473906d4ea259f5ff0abf39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaab914937d473906d4ea259f5ff0abf39">XRFDC_TISK_DAC0_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaab914937d473906d4ea259f5ff0abf39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch0 front end switch0.  <a href="group___overview.html#gaab914937d473906d4ea259f5ff0abf39">More...</a><br/></td></tr>
<tr class="separator:gaab914937d473906d4ea259f5ff0abf39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf292ffc81464ad33333d533cc18f9d37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf292ffc81464ad33333d533cc18f9d37">XRFDC_TISK_DAC0_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gaf292ffc81464ad33333d533cc18f9d37"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#gaf292ffc81464ad33333d533cc18f9d37">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DAC1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch1.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga47f4bd06551df3aa7d0f029c97a8b3be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga47f4bd06551df3aa7d0f029c97a8b3be">XRFDC_TISK_DAC1_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga47f4bd06551df3aa7d0f029c97a8b3be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch1 front end switch0.  <a href="group___overview.html#ga47f4bd06551df3aa7d0f029c97a8b3be">More...</a><br/></td></tr>
<tr class="separator:ga47f4bd06551df3aa7d0f029c97a8b3be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae6550e1ac20e14ea920f8153944b2fcd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae6550e1ac20e14ea920f8153944b2fcd">XRFDC_TISK_DAC1_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gae6550e1ac20e14ea920f8153944b2fcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#gae6550e1ac20e14ea920f8153944b2fcd">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DAC2</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch2.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga48a11bae2d84dfb2295ed6a36867265c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga48a11bae2d84dfb2295ed6a36867265c">XRFDC_TISK_DAC2_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga48a11bae2d84dfb2295ed6a36867265c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch2 front end switch0.  <a href="group___overview.html#ga48a11bae2d84dfb2295ed6a36867265c">More...</a><br/></td></tr>
<tr class="separator:ga48a11bae2d84dfb2295ed6a36867265c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7deb1b799a85477dddd294bb39741f90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7deb1b799a85477dddd294bb39741f90">XRFDC_TISK_DAC2_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga7deb1b799a85477dddd294bb39741f90"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#ga7deb1b799a85477dddd294bb39741f90">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DAC3</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch3.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga2b600795b05dc1a3cfab6e0bab77ff73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2b600795b05dc1a3cfab6e0bab77ff73">XRFDC_TISK_DAC3_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga2b600795b05dc1a3cfab6e0bab77ff73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch3 front end switch0.  <a href="group___overview.html#ga2b600795b05dc1a3cfab6e0bab77ff73">More...</a><br/></td></tr>
<tr class="separator:ga2b600795b05dc1a3cfab6e0bab77ff73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga213a91213fd35035976e065195733f42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga213a91213fd35035976e065195733f42">XRFDC_TISK_DAC3_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga213a91213fd35035976e065195733f42"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#ga213a91213fd35035976e065195733f42">More...</a><br/></td></tr>
<tr class="separator:ga213a91213fd35035976e065195733f42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI Time Skew DACP0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch0.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga29b3b2837c679cfa97af0eb025e8346e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga29b3b2837c679cfa97af0eb025e8346e">XRFDC_TISK_DACP0_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga29b3b2837c679cfa97af0eb025e8346e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch0 front end switch1.  <a href="group___overview.html#ga29b3b2837c679cfa97af0eb025e8346e">More...</a><br/></td></tr>
<tr class="separator:ga29b3b2837c679cfa97af0eb025e8346e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40022dd3c91e5cba28e3322ab33b75ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga40022dd3c91e5cba28e3322ab33b75ab">XRFDC_TISK_DACP0_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga40022dd3c91e5cba28e3322ab33b75ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#ga40022dd3c91e5cba28e3322ab33b75ab">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DACP1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch1.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga37db0c07bb0ece9ef52e9338de3f870a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga37db0c07bb0ece9ef52e9338de3f870a">XRFDC_TISK_DACP1_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga37db0c07bb0ece9ef52e9338de3f870a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch1 front end switch1.  <a href="group___overview.html#ga37db0c07bb0ece9ef52e9338de3f870a">More...</a><br/></td></tr>
<tr class="separator:ga37db0c07bb0ece9ef52e9338de3f870a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03d202dc250b81219d28e92627c05042"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03d202dc250b81219d28e92627c05042">XRFDC_TISK_DACP1_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga03d202dc250b81219d28e92627c05042"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#ga03d202dc250b81219d28e92627c05042">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DACP2</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch2.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf2c8d2e1141425bcd00d6762ef63d2a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf2c8d2e1141425bcd00d6762ef63d2a0">XRFDC_TISK_DACP2_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaf2c8d2e1141425bcd00d6762ef63d2a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch2 front end switch1.  <a href="group___overview.html#gaf2c8d2e1141425bcd00d6762ef63d2a0">More...</a><br/></td></tr>
<tr class="separator:gaf2c8d2e1141425bcd00d6762ef63d2a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c78e64e8ad4ad79c978094967342ee9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5c78e64e8ad4ad79c978094967342ee9">XRFDC_TISK_DACP2_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga5c78e64e8ad4ad79c978094967342ee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#ga5c78e64e8ad4ad79c978094967342ee9">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">TI Time Skew DACP3</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for Time skew DAC cal code of subadc ch3.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf41c2e8bb1730dfc33817cc001cdb416"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf41c2e8bb1730dfc33817cc001cdb416">XRFDC_TISK_DACP3_CODE_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaf41c2e8bb1730dfc33817cc001cdb416"><td class="mdescLeft">&#160;</td><td class="mdescRight">Code to correction DAC of subadc ch3 front end switch1.  <a href="group___overview.html#gaf41c2e8bb1730dfc33817cc001cdb416">More...</a><br/></td></tr>
<tr class="separator:gaf41c2e8bb1730dfc33817cc001cdb416"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae18854cb77722b9e92d43ddaac77f65"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaae18854cb77722b9e92d43ddaac77f65">XRFDC_TISK_DACP3_OVRID_EN_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gaae18854cb77722b9e92d43ddaac77f65"><td class="mdescLeft">&#160;</td><td class="mdescRight">override enable  <a href="group___overview.html#gaae18854cb77722b9e92d43ddaac77f65">More...</a><br/></td></tr>
<tr class="separator:gaae18854cb77722b9e92d43ddaac77f65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC0 address</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp address of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga012fadbcbb766ec2add444ac0eaa456b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga012fadbcbb766ec2add444ac0eaa456b">XRFDC_SUBDRP_ADC0_ADDR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga012fadbcbb766ec2add444ac0eaa456b"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp0 address  <a href="group___overview.html#ga012fadbcbb766ec2add444ac0eaa456b">More...</a><br/></td></tr>
<tr class="separator:ga012fadbcbb766ec2add444ac0eaa456b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC0 Data</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp data of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga301d2b13220acaf2bdcb62b7c9aa362c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga301d2b13220acaf2bdcb62b7c9aa362c">XRFDC_SUBDRP_ADC0_DAT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga301d2b13220acaf2bdcb62b7c9aa362c"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp0 data for read or write transaction  <a href="group___overview.html#ga301d2b13220acaf2bdcb62b7c9aa362c">More...</a><br/></td></tr>
<tr class="separator:ga301d2b13220acaf2bdcb62b7c9aa362c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC1 address</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp address of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga74fd465c9fbf4f3785bfdbd535f3bf37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga74fd465c9fbf4f3785bfdbd535f3bf37">XRFDC_SUBDRP_ADC1_ADDR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga74fd465c9fbf4f3785bfdbd535f3bf37"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp1 address  <a href="group___overview.html#ga74fd465c9fbf4f3785bfdbd535f3bf37">More...</a><br/></td></tr>
<tr class="separator:ga74fd465c9fbf4f3785bfdbd535f3bf37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC1 Data</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp data of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gac3f2da59d0804fecce382d0fa34e00ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac3f2da59d0804fecce382d0fa34e00ec">XRFDC_SUBDRP_ADC1_DAT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gac3f2da59d0804fecce382d0fa34e00ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp1 data for read or write transaction  <a href="group___overview.html#gac3f2da59d0804fecce382d0fa34e00ec">More...</a><br/></td></tr>
<tr class="separator:gac3f2da59d0804fecce382d0fa34e00ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC2 address</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp address of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga670847a150bb7f03a3f9bed349550539"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga670847a150bb7f03a3f9bed349550539">XRFDC_SUBDRP_ADC2_ADDR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga670847a150bb7f03a3f9bed349550539"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp2 address  <a href="group___overview.html#ga670847a150bb7f03a3f9bed349550539">More...</a><br/></td></tr>
<tr class="separator:ga670847a150bb7f03a3f9bed349550539"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC2 Data</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp data of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga5e8e723966c418df2dcce6ea3fd4452e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5e8e723966c418df2dcce6ea3fd4452e">XRFDC_SUBDRP_ADC2_DAT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga5e8e723966c418df2dcce6ea3fd4452e"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp2 data for read or write transaction  <a href="group___overview.html#ga5e8e723966c418df2dcce6ea3fd4452e">More...</a><br/></td></tr>
<tr class="separator:ga5e8e723966c418df2dcce6ea3fd4452e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC3 address</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp address of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaebdd74258ec8c93bc90c8d0bf5b9d021"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaebdd74258ec8c93bc90c8d0bf5b9d021">XRFDC_SUBDRP_ADC3_ADDR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaebdd74258ec8c93bc90c8d0bf5b9d021"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp3 address  <a href="group___overview.html#gaebdd74258ec8c93bc90c8d0bf5b9d021">More...</a><br/></td></tr>
<tr class="separator:gaebdd74258ec8c93bc90c8d0bf5b9d021"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SubDRP ADC3 Data</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the sub-drp data of the target register.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga1469b0f8e7e2629e8b581178aae263c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1469b0f8e7e2629e8b581178aae263c8">XRFDC_SUBDRP_ADC3_DAT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga1469b0f8e7e2629e8b581178aae263c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">sub-drp3 data for read or write transaction  <a href="group___overview.html#ga1469b0f8e7e2629e8b581178aae263c8">More...</a><br/></td></tr>
<tr class="separator:ga1469b0f8e7e2629e8b581178aae263c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX MC PWRDWN</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga3757eea7968bf725b0b8472192a04a4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3757eea7968bf725b0b8472192a04a4a">XRFDC_RX_MC_PWRDWN_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga3757eea7968bf725b0b8472192a04a4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX MC power down.  <a href="group___overview.html#ga3757eea7968bf725b0b8472192a04a4a">More...</a><br/></td></tr>
<tr class="separator:ga3757eea7968bf725b0b8472192a04a4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX MC Config0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gafbf06da8fe294d384ffd2efd99da2243"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafbf06da8fe294d384ffd2efd99da2243">XRFDC_RX_MC_CFG0_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gafbf06da8fe294d384ffd2efd99da2243"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX MC config0.  <a href="group___overview.html#gafbf06da8fe294d384ffd2efd99da2243">More...</a><br/></td></tr>
<tr class="separator:gafbf06da8fe294d384ffd2efd99da2243"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7de28176dd2971866c8929e8f9e712c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7de28176dd2971866c8929e8f9e712c6">XRFDC_RX_MC_CFG0_CM_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga7de28176dd2971866c8929e8f9e712c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coupling mode mask.  <a href="group___overview.html#ga7de28176dd2971866c8929e8f9e712c6">More...</a><br/></td></tr>
<tr class="separator:ga7de28176dd2971866c8929e8f9e712c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80883b0a5fe9ca4aeb216f49c1a283b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga80883b0a5fe9ca4aeb216f49c1a283b2">XRFDC_RX_MC_CFG0_IM3_DITH_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga80883b0a5fe9ca4aeb216f49c1a283b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">IM3 Dither Enable mode mask.  <a href="group___overview.html#ga80883b0a5fe9ca4aeb216f49c1a283b2">More...</a><br/></td></tr>
<tr class="separator:ga80883b0a5fe9ca4aeb216f49c1a283b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6fe6b193044b79c052f9ca142cfbdef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf6fe6b193044b79c052f9ca142cfbdef">XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT</a>&#160;&#160;&#160;5U</td></tr>
<tr class="memdesc:gaf6fe6b193044b79c052f9ca142cfbdef"><td class="mdescLeft">&#160;</td><td class="mdescRight">IM3 Dither Enable mode shift.  <a href="group___overview.html#gaf6fe6b193044b79c052f9ca142cfbdef">More...</a><br/></td></tr>
<tr class="separator:gaf6fe6b193044b79c052f9ca142cfbdef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX MC Config1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga9cdfbadfe68a2c4c3dd7a72d93623c4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9cdfbadfe68a2c4c3dd7a72d93623c4c">XRFDC_RX_MC_CFG1_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga9cdfbadfe68a2c4c3dd7a72d93623c4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX MC Config1.  <a href="group___overview.html#ga9cdfbadfe68a2c4c3dd7a72d93623c4c">More...</a><br/></td></tr>
<tr class="separator:ga9cdfbadfe68a2c4c3dd7a72d93623c4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX MC Config2</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga8949944a2e236dc0e7afb671997c4800"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8949944a2e236dc0e7afb671997c4800">XRFDC_RX_MC_CFG2_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga8949944a2e236dc0e7afb671997c4800"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX MC Config2.  <a href="group___overview.html#ga8949944a2e236dc0e7afb671997c4800">More...</a><br/></td></tr>
<tr class="separator:ga8949944a2e236dc0e7afb671997c4800"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX Pair MC Config0</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf7e3aadf4c9e7a10ab3fcfd65bac7dbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf7e3aadf4c9e7a10ab3fcfd65bac7dbb">XRFDC_RX_PR_MC_CFG0_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaf7e3aadf4c9e7a10ab3fcfd65bac7dbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Pair MC Config0.  <a href="group___overview.html#gaf7e3aadf4c9e7a10ab3fcfd65bac7dbb">More...</a><br/></td></tr>
<tr class="separator:gaf7e3aadf4c9e7a10ab3fcfd65bac7dbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a6e055a80e74687242263f9e3611ff9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a6e055a80e74687242263f9e3611ff9">XRFDC_RX_PR_MC_CFG0_PSNK_MASK</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:ga9a6e055a80e74687242263f9e3611ff9"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Pair MC Config0.  <a href="group___overview.html#ga9a6e055a80e74687242263f9e3611ff9">More...</a><br/></td></tr>
<tr class="separator:ga9a6e055a80e74687242263f9e3611ff9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27c98ac0e35796caf4e7780d3d8654ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga27c98ac0e35796caf4e7780d3d8654ad">XRFDC_RX_PR_MC_CFG0_IDIV_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga27c98ac0e35796caf4e7780d3d8654ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Pair MC Config0.  <a href="group___overview.html#ga27c98ac0e35796caf4e7780d3d8654ad">More...</a><br/></td></tr>
<tr class="separator:ga27c98ac0e35796caf4e7780d3d8654ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">RX Pair MC Config1</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gabac7cf77b24d57c4af0337e180d4e456"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabac7cf77b24d57c4af0337e180d4e456">XRFDC_RX_PR_MC_CFG1_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gabac7cf77b24d57c4af0337e180d4e456"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Pair MC Config1.  <a href="group___overview.html#gabac7cf77b24d57c4af0337e180d4e456">More...</a><br/></td></tr>
<tr class="separator:gabac7cf77b24d57c4af0337e180d4e456"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status0 BG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch0 ocb1 BG offset correction factor value.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga4a7e0cdf402970dd7f481eff3de9fff6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4a7e0cdf402970dd7f481eff3de9fff6">XRFDC_TI_DCB_STS0_BG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga4a7e0cdf402970dd7f481eff3de9fff6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status0 BG.  <a href="group___overview.html#ga4a7e0cdf402970dd7f481eff3de9fff6">More...</a><br/></td></tr>
<tr class="separator:ga4a7e0cdf402970dd7f481eff3de9fff6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status0 FG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch0 ocb2 FG offset correction factor value(read and write).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga59063656af39679671c806b07ca46174"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga59063656af39679671c806b07ca46174">XRFDC_TI_DCB_STS0_FG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga59063656af39679671c806b07ca46174"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status0 FG.  <a href="group___overview.html#ga59063656af39679671c806b07ca46174">More...</a><br/></td></tr>
<tr class="separator:ga59063656af39679671c806b07ca46174"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status1 BG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch1 ocb1 BG offset correction factor value.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga2fce7525519fce52ae13b76f481f97a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2fce7525519fce52ae13b76f481f97a7">XRFDC_TI_DCB_STS1_BG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga2fce7525519fce52ae13b76f481f97a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status1 BG.  <a href="group___overview.html#ga2fce7525519fce52ae13b76f481f97a7">More...</a><br/></td></tr>
<tr class="separator:ga2fce7525519fce52ae13b76f481f97a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status1 FG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch1 ocb2 FG offset correction factor value(read and write).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf3dbc3bbb03d9739076c12e80f2fa34f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf3dbc3bbb03d9739076c12e80f2fa34f">XRFDC_TI_DCB_STS1_FG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaf3dbc3bbb03d9739076c12e80f2fa34f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status1 FG.  <a href="group___overview.html#gaf3dbc3bbb03d9739076c12e80f2fa34f">More...</a><br/></td></tr>
<tr class="separator:gaf3dbc3bbb03d9739076c12e80f2fa34f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status2 BG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch2 ocb1 BG offset correction factor value.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaa395ce988844aed41583b3fae3d69a15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa395ce988844aed41583b3fae3d69a15">XRFDC_TI_DCB_STS2_BG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaa395ce988844aed41583b3fae3d69a15"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status2 BG.  <a href="group___overview.html#gaa395ce988844aed41583b3fae3d69a15">More...</a><br/></td></tr>
<tr class="separator:gaa395ce988844aed41583b3fae3d69a15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status2 FG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch2 ocb2 FG offset correction factor value(read and write).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaa712d67664cf1861fb6c2d2f77b4e492"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa712d67664cf1861fb6c2d2f77b4e492">XRFDC_TI_DCB_STS2_FG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaa712d67664cf1861fb6c2d2f77b4e492"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status2 FG.  <a href="group___overview.html#gaa712d67664cf1861fb6c2d2f77b4e492">More...</a><br/></td></tr>
<tr class="separator:gaa712d67664cf1861fb6c2d2f77b4e492"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status3 BG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch3 ocb1 BG offset correction factor value.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga8d447d94259702787da6d10e69ad3153"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8d447d94259702787da6d10e69ad3153">XRFDC_TI_DCB_STS3_BG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga8d447d94259702787da6d10e69ad3153"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status3 BG.  <a href="group___overview.html#ga8d447d94259702787da6d10e69ad3153">More...</a><br/></td></tr>
<tr class="separator:ga8d447d94259702787da6d10e69ad3153"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status3 FG</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the subadc ch3 ocb2 FG offset correction factor value(read and write).</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga044e1364844a6229858c4bf78c7e2e56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga044e1364844a6229858c4bf78c7e2e56">XRFDC_TI_DCB_STS3_FG_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga044e1364844a6229858c4bf78c7e2e56"><td class="mdescLeft">&#160;</td><td class="mdescRight">DCB Status3 FG.  <a href="group___overview.html#ga044e1364844a6229858c4bf78c7e2e56">More...</a><br/></td></tr>
<tr class="separator:ga044e1364844a6229858c4bf78c7e2e56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status4 MSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaf5e6181b155be7c06573d0fa835abdb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf5e6181b155be7c06573d0fa835abdb0">XRFDC_TI_DCB_STS4_MSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaf5e6181b155be7c06573d0fa835abdb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc0 msb bits(subadc chan0)  <a href="group___overview.html#gaf5e6181b155be7c06573d0fa835abdb0">More...</a><br/></td></tr>
<tr class="separator:gaf5e6181b155be7c06573d0fa835abdb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status4 LSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB Status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga04789c6ca6a64be7dfcdcdc7e5a77a04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga04789c6ca6a64be7dfcdcdc7e5a77a04">XRFDC_TI_DCB_STS4_LSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga04789c6ca6a64be7dfcdcdc7e5a77a04"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc0 lsb bits(subadc chan0)  <a href="group___overview.html#ga04789c6ca6a64be7dfcdcdc7e5a77a04">More...</a><br/></td></tr>
<tr class="separator:ga04789c6ca6a64be7dfcdcdc7e5a77a04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status5 MSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:gaccfdf05cce89d0137d52febdc7875260"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaccfdf05cce89d0137d52febdc7875260">XRFDC_TI_DCB_STS5_MSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaccfdf05cce89d0137d52febdc7875260"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc1 msb bits(subadc chan1)  <a href="group___overview.html#gaccfdf05cce89d0137d52febdc7875260">More...</a><br/></td></tr>
<tr class="separator:gaccfdf05cce89d0137d52febdc7875260"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status5 LSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB Status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga05b0358cdb732b17e01f78d40a5cc39f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga05b0358cdb732b17e01f78d40a5cc39f">XRFDC_TI_DCB_STS5_LSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga05b0358cdb732b17e01f78d40a5cc39f"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc1 lsb bits(subadc chan1)  <a href="group___overview.html#ga05b0358cdb732b17e01f78d40a5cc39f">More...</a><br/></td></tr>
<tr class="separator:ga05b0358cdb732b17e01f78d40a5cc39f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status6 MSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga7d3da2aaff966ba6d3e64a3cbd518b0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7d3da2aaff966ba6d3e64a3cbd518b0a">XRFDC_TI_DCB_STS6_MSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga7d3da2aaff966ba6d3e64a3cbd518b0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc2 msb bits(subadc chan2)  <a href="group___overview.html#ga7d3da2aaff966ba6d3e64a3cbd518b0a">More...</a><br/></td></tr>
<tr class="separator:ga7d3da2aaff966ba6d3e64a3cbd518b0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status6 LSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB Status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga91b0f6cf2f111f3c3e4ef3491ca2017a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga91b0f6cf2f111f3c3e4ef3491ca2017a">XRFDC_TI_DCB_STS6_LSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga91b0f6cf2f111f3c3e4ef3491ca2017a"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc2 lsb bits(subadc chan2)  <a href="group___overview.html#ga91b0f6cf2f111f3c3e4ef3491ca2017a">More...</a><br/></td></tr>
<tr class="separator:ga91b0f6cf2f111f3c3e4ef3491ca2017a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status7 MSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga009f0258bfe52af132e15cd2dd18f31c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga009f0258bfe52af132e15cd2dd18f31c">XRFDC_TI_DCB_STS7_MSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga009f0258bfe52af132e15cd2dd18f31c"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc3 msb bits(subadc chan3)  <a href="group___overview.html#ga009f0258bfe52af132e15cd2dd18f31c">More...</a><br/></td></tr>
<tr class="separator:ga009f0258bfe52af132e15cd2dd18f31c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TI DCB Status7 LSB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the DCB Status.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga00c3645e4f6e59635a3974b98a4a8910"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga00c3645e4f6e59635a3974b98a4a8910">XRFDC_TI_DCB_STS7_LSB_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga00c3645e4f6e59635a3974b98a4a8910"><td class="mdescLeft">&#160;</td><td class="mdescRight">read the status of gcb acc3 lsb bits(subadc chan3)  <a href="group___overview.html#ga00c3645e4f6e59635a3974b98a4a8910">More...</a><br/></td></tr>
<tr class="separator:ga00c3645e4f6e59635a3974b98a4a8910"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">PLL_REFDIV</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the bits for Reference Clock Divider </p>
</div></td></tr>
<tr class="memitem:ga9679c97dee358843048ffc120557b5c2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9679c97dee358843048ffc120557b5c2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_REFCLK_DIV_MASK</b>&#160;&#160;&#160;0x1FU</td></tr>
<tr class="separator:ga9679c97dee358843048ffc120557b5c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ed25b746e934ee51b87a576731ffe04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9ed25b746e934ee51b87a576731ffe04">XRFDC_REFCLK_DIV_1_MASK</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga9ed25b746e934ee51b87a576731ffe04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Div1.  <a href="group___overview.html#ga9ed25b746e934ee51b87a576731ffe04">More...</a><br/></td></tr>
<tr class="separator:ga9ed25b746e934ee51b87a576731ffe04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac505119d79bfa1c67510e54ae0c7dd3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac505119d79bfa1c67510e54ae0c7dd3a">XRFDC_REFCLK_DIV_2_MASK</a>&#160;&#160;&#160;0x0U</td></tr>
<tr class="memdesc:gac505119d79bfa1c67510e54ae0c7dd3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Div2.  <a href="group___overview.html#gac505119d79bfa1c67510e54ae0c7dd3a">More...</a><br/></td></tr>
<tr class="separator:gac505119d79bfa1c67510e54ae0c7dd3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e90507e8bed1423d63f8f8f18b4f409"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e90507e8bed1423d63f8f8f18b4f409">XRFDC_REFCLK_DIV_3_MASK</a>&#160;&#160;&#160;0x1U</td></tr>
<tr class="memdesc:ga7e90507e8bed1423d63f8f8f18b4f409"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Div3.  <a href="group___overview.html#ga7e90507e8bed1423d63f8f8f18b4f409">More...</a><br/></td></tr>
<tr class="separator:ga7e90507e8bed1423d63f8f8f18b4f409"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a5e0527469e5de3dec0e2f95d19a452"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a5e0527469e5de3dec0e2f95d19a452">XRFDC_REFCLK_DIV_4_MASK</a>&#160;&#160;&#160;0x2U</td></tr>
<tr class="memdesc:ga9a5e0527469e5de3dec0e2f95d19a452"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Div4.  <a href="group___overview.html#ga9a5e0527469e5de3dec0e2f95d19a452">More...</a><br/></td></tr>
<tr class="separator:ga9a5e0527469e5de3dec0e2f95d19a452"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Latency</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for result, key and done flag.</p>
<p>Read/Write apart from the reserved bits. </p>
</div></td></tr>
<tr class="memitem:ga91b310627f6be2f611776018aeb4be6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga91b310627f6be2f611776018aeb4be6f">XRFDC_FIFO_LTNCY_RES_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:ga91b310627f6be2f611776018aeb4be6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latency measurement result.  <a href="group___overview.html#ga91b310627f6be2f611776018aeb4be6f">More...</a><br/></td></tr>
<tr class="separator:ga91b310627f6be2f611776018aeb4be6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga494d6ce3625323eae8e66511b8c99e3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga494d6ce3625323eae8e66511b8c99e3c">XRFDC_FIFO_LTNCY_KEY_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:ga494d6ce3625323eae8e66511b8c99e3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latency measurement result identification key.  <a href="group___overview.html#ga494d6ce3625323eae8e66511b8c99e3c">More...</a><br/></td></tr>
<tr class="separator:ga494d6ce3625323eae8e66511b8c99e3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf98711ba31cf3063c00f2c59474a51a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf98711ba31cf3063c00f2c59474a51a0">XRFDC_FIFO_LTNCY_DONE_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gaf98711ba31cf3063c00f2c59474a51a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Latency measurement done flag.  <a href="group___overview.html#gaf98711ba31cf3063c00f2c59474a51a0">More...</a><br/></td></tr>
<tr class="separator:gaf98711ba31cf3063c00f2c59474a51a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Decoder Control</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Unary Decoder/Randomizer settings to use. </p>
</div></td></tr>
<tr class="memitem:ga4943231bb1c45629dd4d300f9b0d8814"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4943231bb1c45629dd4d300f9b0d8814">XRFDC_DEC_CTRL_MODE_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga4943231bb1c45629dd4d300f9b0d8814"><td class="mdescLeft">&#160;</td><td class="mdescRight">Decoder mode.  <a href="group___overview.html#ga4943231bb1c45629dd4d300f9b0d8814">More...</a><br/></td></tr>
<tr class="separator:ga4943231bb1c45629dd4d300f9b0d8814"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HSCOM Power state mask</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains HSCOM_PWR to check powerup_state. </p>
</div></td></tr>
<tr class="memitem:gae433658d7812df938d1c778427bac9ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae433658d7812df938d1c778427bac9ac">XRFDC_HSCOM_PWR_STATE_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gae433658d7812df938d1c778427bac9ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">powerup state mask  <a href="group___overview.html#gae433658d7812df938d1c778427bac9ac">More...</a><br/></td></tr>
<tr class="separator:gae433658d7812df938d1c778427bac9ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interpolation Control</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Interpolation filter modes. </p>
</div></td></tr>
<tr class="memitem:ga2666ef5dd0f3aa8dc1fb8110030b1873"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2666ef5dd0f3aa8dc1fb8110030b1873">XRFDC_INTERP_MODE_MASK</a>&#160;&#160;&#160;0x00000077U</td></tr>
<tr class="memdesc:ga2666ef5dd0f3aa8dc1fb8110030b1873"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp filter mask.  <a href="group___overview.html#ga2666ef5dd0f3aa8dc1fb8110030b1873">More...</a><br/></td></tr>
<tr class="separator:ga2666ef5dd0f3aa8dc1fb8110030b1873"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2ff27d5d05da2bb877985d5f4f23aaf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2ff27d5d05da2bb877985d5f4f23aaf2">XRFDC_INTERP_MODE_I_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga2ff27d5d05da2bb877985d5f4f23aaf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp filter I.  <a href="group___overview.html#ga2ff27d5d05da2bb877985d5f4f23aaf2">More...</a><br/></td></tr>
<tr class="separator:ga2ff27d5d05da2bb877985d5f4f23aaf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa81ed15ff245d9830a7e35bca520cf59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa81ed15ff245d9830a7e35bca520cf59">XRFDC_INTERP_MODE_Q_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:gaa81ed15ff245d9830a7e35bca520cf59"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp mode Q shift.  <a href="group___overview.html#gaa81ed15ff245d9830a7e35bca520cf59">More...</a><br/></td></tr>
<tr class="separator:gaa81ed15ff245d9830a7e35bca520cf59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb95c91e5245e2dae6b1a50dc4d773fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadb95c91e5245e2dae6b1a50dc4d773fc">XRFDC_INTERP_MODE_MASK_EXT</a>&#160;&#160;&#160;0x00003F3FU</td></tr>
<tr class="memdesc:gadb95c91e5245e2dae6b1a50dc4d773fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp filter mask.  <a href="group___overview.html#gadb95c91e5245e2dae6b1a50dc4d773fc">More...</a><br/></td></tr>
<tr class="separator:gadb95c91e5245e2dae6b1a50dc4d773fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67e9bed4914d5b35ffed701dde3f0871"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga67e9bed4914d5b35ffed701dde3f0871">XRFDC_INTERP_MODE_I_MASK_EXT</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga67e9bed4914d5b35ffed701dde3f0871"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp filter I.  <a href="group___overview.html#ga67e9bed4914d5b35ffed701dde3f0871">More...</a><br/></td></tr>
<tr class="separator:ga67e9bed4914d5b35ffed701dde3f0871"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9202860f0ef0efce9bacf9df483ce3c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9202860f0ef0efce9bacf9df483ce3c0">XRFDC_INTERP_MODE_Q_SHIFT_EXT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga9202860f0ef0efce9bacf9df483ce3c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interp mode Q shift.  <a href="group___overview.html#ga9202860f0ef0efce9bacf9df483ce3c0">More...</a><br/></td></tr>
<tr class="separator:ga9202860f0ef0efce9bacf9df483ce3c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Tile enables register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the bits that indicate whether or not a tile is enabled (Read Only). </p>
</div></td></tr>
<tr class="memitem:ga517cadb745c3a9bb600c32149f3a0972"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga517cadb745c3a9bb600c32149f3a0972">XRFDC_DAC_TILES_ENABLED_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:ga517cadb745c3a9bb600c32149f3a0972"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift to the DAC tile bits.  <a href="group___overview.html#ga517cadb745c3a9bb600c32149f3a0972">More...</a><br/></td></tr>
<tr class="separator:ga517cadb745c3a9bb600c32149f3a0972"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Path enables register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the bits that indicate whether or not an analogue/digital is enabled (Read Only). </p>
</div></td></tr>
<tr class="memitem:ga9a3a831102bb3232d96c95f966777ca4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a3a831102bb3232d96c95f966777ca4">XRFDC_DIGITAL_PATH_ENABLED_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:ga9a3a831102bb3232d96c95f966777ca4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift to the digital path bits.  <a href="group___overview.html#ga9a3a831102bb3232d96c95f966777ca4">More...</a><br/></td></tr>
<tr class="separator:ga9a3a831102bb3232d96c95f966777ca4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Tile Reset</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Tile reset bit. </p>
</div></td></tr>
<tr class="memitem:ga7441efc7f45b5fb0f6e80ae442d28e90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7441efc7f45b5fb0f6e80ae442d28e90">XRFDC_TILE_RESET_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga7441efc7f45b5fb0f6e80ae442d28e90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tile reset mask.  <a href="group___overview.html#ga7441efc7f45b5fb0f6e80ae442d28e90">More...</a><br/></td></tr>
<tr class="separator:ga7441efc7f45b5fb0f6e80ae442d28e90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains common status bits. </p>
</div></td></tr>
<tr class="memitem:ga63859c46a8dfa58718901c92a6f60120"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga63859c46a8dfa58718901c92a6f60120">XRFDC_PWR_UP_STAT_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga63859c46a8dfa58718901c92a6f60120"><td class="mdescLeft">&#160;</td><td class="mdescRight">Power Up state mask.  <a href="group___overview.html#ga63859c46a8dfa58718901c92a6f60120">More...</a><br/></td></tr>
<tr class="separator:ga63859c46a8dfa58718901c92a6f60120"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeecb7f81e47e0daf39ca3077b860292c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaeecb7f81e47e0daf39ca3077b860292c">XRFDC_PWR_UP_STAT_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gaeecb7f81e47e0daf39ca3077b860292c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PowerUp status shift.  <a href="group___overview.html#gaeecb7f81e47e0daf39ca3077b860292c">More...</a><br/></td></tr>
<tr class="separator:gaeecb7f81e47e0daf39ca3077b860292c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a6fbbcb2c3a787b858d360305c199e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a6fbbcb2c3a787b858d360305c199e0">XRFDC_PLL_LOCKED_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga0a6fbbcb2c3a787b858d360305c199e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL Locked mask.  <a href="group___overview.html#ga0a6fbbcb2c3a787b858d360305c199e0">More...</a><br/></td></tr>
<tr class="separator:ga0a6fbbcb2c3a787b858d360305c199e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb0e065e20b51688b0a99b9534752cec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadb0e065e20b51688b0a99b9534752cec">XRFDC_PLL_LOCKED_SHIFT</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:gadb0e065e20b51688b0a99b9534752cec"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL locked shift.  <a href="group___overview.html#gadb0e065e20b51688b0a99b9534752cec">More...</a><br/></td></tr>
<tr class="separator:gadb0e065e20b51688b0a99b9534752cec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Restart State register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Start and End state bits. </p>
</div></td></tr>
<tr class="memitem:gad6c44d9b8b53f010b163b90ed955bdce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad6c44d9b8b53f010b163b90ed955bdce">XRFDC_PWR_STATE_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gad6c44d9b8b53f010b163b90ed955bdce"><td class="mdescLeft">&#160;</td><td class="mdescRight">State mask.  <a href="group___overview.html#gad6c44d9b8b53f010b163b90ed955bdce">More...</a><br/></td></tr>
<tr class="separator:gad6c44d9b8b53f010b163b90ed955bdce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee4b3e27a89d7f6b5a1e97bf13489b24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaee4b3e27a89d7f6b5a1e97bf13489b24">XRFDC_RSR_START_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:gaee4b3e27a89d7f6b5a1e97bf13489b24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start state shift.  <a href="group___overview.html#gaee4b3e27a89d7f6b5a1e97bf13489b24">More...</a><br/></td></tr>
<tr class="separator:gaee4b3e27a89d7f6b5a1e97bf13489b24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock Detect register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Start and End state bits. </p>
</div></td></tr>
<tr class="memitem:ga6f17a55cd1ee6539c046f8062e691600"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6f17a55cd1ee6539c046f8062e691600">XRFDC_CLOCK_DETECT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga6f17a55cd1ee6539c046f8062e691600"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock detect mask.  <a href="group___overview.html#ga6f17a55cd1ee6539c046f8062e691600">More...</a><br/></td></tr>
<tr class="separator:ga6f17a55cd1ee6539c046f8062e691600"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadddfabf6192c0cbaf505db355cf5fdd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadddfabf6192c0cbaf505db355cf5fdd2">XRFDC_CLOCK_DETECT_SRC_MASK</a>&#160;&#160;&#160;0x00005555U</td></tr>
<tr class="memdesc:gadddfabf6192c0cbaf505db355cf5fdd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock detect mask.  <a href="group___overview.html#gadddfabf6192c0cbaf505db355cf5fdd2">More...</a><br/></td></tr>
<tr class="separator:gadddfabf6192c0cbaf505db355cf5fdd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae03952a891304ab98fd609005eccb3f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae03952a891304ab98fd609005eccb3f3">XRFDC_CLOCK_DETECT_DST_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:gae03952a891304ab98fd609005eccb3f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock detect mask.  <a href="group___overview.html#gae03952a891304ab98fd609005eccb3f3">More...</a><br/></td></tr>
<tr class="separator:gae03952a891304ab98fd609005eccb3f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Common interrupt enable register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to enable interrupt for ADC and DAC tiles. </p>
</div></td></tr>
<tr class="memitem:ga317da2c63928b37f9bb42b4d495d8cb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga317da2c63928b37f9bb42b4d495d8cb7">XRFDC_EN_INTR_DAC_TILE0_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga317da2c63928b37f9bb42b4d495d8cb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Tile0 interrupt enable mask.  <a href="group___overview.html#ga317da2c63928b37f9bb42b4d495d8cb7">More...</a><br/></td></tr>
<tr class="separator:ga317da2c63928b37f9bb42b4d495d8cb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c0d6ec0c0b66319aaed16e5d96e3d2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0c0d6ec0c0b66319aaed16e5d96e3d2e">XRFDC_EN_INTR_DAC_TILE1_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga0c0d6ec0c0b66319aaed16e5d96e3d2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Tile1 interrupt enable mask.  <a href="group___overview.html#ga0c0d6ec0c0b66319aaed16e5d96e3d2e">More...</a><br/></td></tr>
<tr class="separator:ga0c0d6ec0c0b66319aaed16e5d96e3d2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbee37ae1d1fcc53480fe4723cd7ae7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacbee37ae1d1fcc53480fe4723cd7ae7a">XRFDC_EN_INTR_DAC_TILE2_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gacbee37ae1d1fcc53480fe4723cd7ae7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Tile2 interrupt enable mask.  <a href="group___overview.html#gacbee37ae1d1fcc53480fe4723cd7ae7a">More...</a><br/></td></tr>
<tr class="separator:gacbee37ae1d1fcc53480fe4723cd7ae7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84efae256203302b458cc24f7c387a41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga84efae256203302b458cc24f7c387a41">XRFDC_EN_INTR_DAC_TILE3_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga84efae256203302b458cc24f7c387a41"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Tile3 interrupt enable mask.  <a href="group___overview.html#ga84efae256203302b458cc24f7c387a41">More...</a><br/></td></tr>
<tr class="separator:ga84efae256203302b458cc24f7c387a41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa32febc88de50e27876951fcef08404"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafa32febc88de50e27876951fcef08404">XRFDC_EN_INTR_ADC_TILE0_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gafa32febc88de50e27876951fcef08404"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Tile0 interrupt enable mask.  <a href="group___overview.html#gafa32febc88de50e27876951fcef08404">More...</a><br/></td></tr>
<tr class="separator:gafa32febc88de50e27876951fcef08404"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4b9481fed6e5a553b55c19d6d7497f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf4b9481fed6e5a553b55c19d6d7497f5">XRFDC_EN_INTR_ADC_TILE1_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaf4b9481fed6e5a553b55c19d6d7497f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Tile1 interrupt enable mask.  <a href="group___overview.html#gaf4b9481fed6e5a553b55c19d6d7497f5">More...</a><br/></td></tr>
<tr class="separator:gaf4b9481fed6e5a553b55c19d6d7497f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01e5540f9f534537423b630e4e54918b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga01e5540f9f534537423b630e4e54918b">XRFDC_EN_INTR_ADC_TILE2_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga01e5540f9f534537423b630e4e54918b"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Tile2 interrupt enable mask.  <a href="group___overview.html#ga01e5540f9f534537423b630e4e54918b">More...</a><br/></td></tr>
<tr class="separator:ga01e5540f9f534537423b630e4e54918b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae958fe3be726be4e084826249f95bd11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae958fe3be726be4e084826249f95bd11">XRFDC_EN_INTR_ADC_TILE3_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gae958fe3be726be4e084826249f95bd11"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Tile3 interrupt enable mask.  <a href="group___overview.html#gae958fe3be726be4e084826249f95bd11">More...</a><br/></td></tr>
<tr class="separator:gae958fe3be726be4e084826249f95bd11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">interrupt enable register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to enable interrupt for blocks. </p>
</div></td></tr>
<tr class="memitem:ga014682b6b373b82fc4b595eee8b10046"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga014682b6b373b82fc4b595eee8b10046">XRFDC_EN_INTR_SLICE_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga014682b6b373b82fc4b595eee8b10046"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slice intr mask.  <a href="group___overview.html#ga014682b6b373b82fc4b595eee8b10046">More...</a><br/></td></tr>
<tr class="separator:ga014682b6b373b82fc4b595eee8b10046"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb35fb75872df53259cc08c082ecf1ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafb35fb75872df53259cc08c082ecf1ce">XRFDC_EN_INTR_SLICE0_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gafb35fb75872df53259cc08c082ecf1ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">slice0 interrupt enable mask  <a href="group___overview.html#gafb35fb75872df53259cc08c082ecf1ce">More...</a><br/></td></tr>
<tr class="separator:gafb35fb75872df53259cc08c082ecf1ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga91727e7dcd3e9b7ec2360600b05009dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga91727e7dcd3e9b7ec2360600b05009dc">XRFDC_EN_INTR_SLICE1_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga91727e7dcd3e9b7ec2360600b05009dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">slice1 interrupt enable mask  <a href="group___overview.html#ga91727e7dcd3e9b7ec2360600b05009dc">More...</a><br/></td></tr>
<tr class="separator:ga91727e7dcd3e9b7ec2360600b05009dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52515a42c8cdc8216a4328a83c87b5f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga52515a42c8cdc8216a4328a83c87b5f1">XRFDC_EN_INTR_SLICE2_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga52515a42c8cdc8216a4328a83c87b5f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">slice2 interrupt enable mask  <a href="group___overview.html#ga52515a42c8cdc8216a4328a83c87b5f1">More...</a><br/></td></tr>
<tr class="separator:ga52515a42c8cdc8216a4328a83c87b5f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2043a5cd71b7082076699190fbbdea2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2043a5cd71b7082076699190fbbdea2c">XRFDC_EN_INTR_SLICE3_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga2043a5cd71b7082076699190fbbdea2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">slice3 interrupt enable mask  <a href="group___overview.html#ga2043a5cd71b7082076699190fbbdea2c">More...</a><br/></td></tr>
<tr class="separator:ga2043a5cd71b7082076699190fbbdea2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga426b3dbef83b0af8b9e8e1cb5ecfb999"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga426b3dbef83b0af8b9e8e1cb5ecfb999">XRFDC_INTR_COMMON_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga426b3dbef83b0af8b9e8e1cb5ecfb999"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common interrupt enable mask.  <a href="group___overview.html#ga426b3dbef83b0af8b9e8e1cb5ecfb999">More...</a><br/></td></tr>
<tr class="separator:ga426b3dbef83b0af8b9e8e1cb5ecfb999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Converter(X) interrupt register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to enable different interrupts for block X. </p>
</div></td></tr>
<tr class="memitem:ga2d07d4776fa647b308501796e1b6ba80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d07d4776fa647b308501796e1b6ba80">XRFDC_INTR_OVR_RANGE_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga2d07d4776fa647b308501796e1b6ba80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over Range interrupt mask.  <a href="group___overview.html#ga2d07d4776fa647b308501796e1b6ba80">More...</a><br/></td></tr>
<tr class="separator:ga2d07d4776fa647b308501796e1b6ba80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0ba9594288ba5b34dad38ad5b99ed9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad0ba9594288ba5b34dad38ad5b99ed9e">XRFDC_INTR_OVR_VOLTAGE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gad0ba9594288ba5b34dad38ad5b99ed9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over Voltage interrupt mask.  <a href="group___overview.html#gad0ba9594288ba5b34dad38ad5b99ed9e">More...</a><br/></td></tr>
<tr class="separator:gad0ba9594288ba5b34dad38ad5b99ed9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11fc5e3d37ec8e5afe801381e5c8dc31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga11fc5e3d37ec8e5afe801381e5c8dc31">XRFDC_INTR_FIFO_OVR_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga11fc5e3d37ec8e5afe801381e5c8dc31"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO OF mask.  <a href="group___overview.html#ga11fc5e3d37ec8e5afe801381e5c8dc31">More...</a><br/></td></tr>
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<tr class="memitem:gafc3ee848501150f1e57d69433a8539fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafc3ee848501150f1e57d69433a8539fe">XRFDC_INTR_DAT_OVR_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:gafc3ee848501150f1e57d69433a8539fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data OF mask.  <a href="group___overview.html#gafc3ee848501150f1e57d69433a8539fe">More...</a><br/></td></tr>
<tr class="separator:gafc3ee848501150f1e57d69433a8539fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65a8fea9a80873a6b18e284f8ec69f73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga65a8fea9a80873a6b18e284f8ec69f73">XRFDC_INTR_CMODE_OVR_MASK</a>&#160;&#160;&#160;0x00040000U</td></tr>
<tr class="memdesc:ga65a8fea9a80873a6b18e284f8ec69f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common mode OV mask.  <a href="group___overview.html#ga65a8fea9a80873a6b18e284f8ec69f73">More...</a><br/></td></tr>
<tr class="separator:ga65a8fea9a80873a6b18e284f8ec69f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1a79b085f96196cd79d2601b97d4b0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad1a79b085f96196cd79d2601b97d4b0a">XRFDC_INTR_CMODE_UNDR_MASK</a>&#160;&#160;&#160;0x00080000U</td></tr>
<tr class="memdesc:gad1a79b085f96196cd79d2601b97d4b0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common mode UV mask.  <a href="group___overview.html#gad1a79b085f96196cd79d2601b97d4b0a">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Multiband config register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure multiband. </p>
</div></td></tr>
<tr class="memitem:gad882c86da84fb558d95d22eb1ce70a2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad882c86da84fb558d95d22eb1ce70a2e">XRFDC_EN_MB_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gad882c86da84fb558d95d22eb1ce70a2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">multi-band adder mask  <a href="group___overview.html#gad882c86da84fb558d95d22eb1ce70a2e">More...</a><br/></td></tr>
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<tr class="memitem:ga9d1722e3bf33c973c43900edbe274c93"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9d1722e3bf33c973c43900edbe274c93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_EN_MB_SHIFT</b>&#160;&#160;&#160;3U /** &lt;Enable Multiband shift */</td></tr>
<tr class="separator:ga9d1722e3bf33c973c43900edbe274c93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec278645409dbd862fd5fcdfef20e461"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaec278645409dbd862fd5fcdfef20e461"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_DAC_MB_SEL_MASK</b>&#160;&#160;&#160;0x0003U /** &lt;Local and remote select mask */</td></tr>
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<tr class="memitem:ga13b7af93bba2a8e99e3ea66cc2c8c191"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga13b7af93bba2a8e99e3ea66cc2c8c191"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_ALT_BOND_MASK</b>&#160;&#160;&#160;0x0200U /** &lt;Alt bondout mask */</td></tr>
<tr class="separator:ga13b7af93bba2a8e99e3ea66cc2c8c191"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd6de2511920d77668edbb5a38798930"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd6de2511920d77668edbb5a38798930"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_ALT_BOND_SHIFT</b>&#160;&#160;&#160;9U /** &lt;Alt bondout shift */</td></tr>
<tr class="separator:gacd6de2511920d77668edbb5a38798930"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae59ee8ddfbd124aa79f433757d985eb5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae59ee8ddfbd124aa79f433757d985eb5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_ALT_BOND_CLKDP_MASK</b>&#160;&#160;&#160;0x4U /** &lt;Alt bondout shift */</td></tr>
<tr class="separator:gae59ee8ddfbd124aa79f433757d985eb5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga186273051ff8a387de11236d21c36d4c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga186273051ff8a387de11236d21c36d4c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_ALT_BOND_CLKDP_SHIFT</b>&#160;&#160;&#160;2U /** &lt;Alt bondout shift */</td></tr>
<tr class="separator:ga186273051ff8a387de11236d21c36d4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga49d5a850eb4a63f35e68de89c446878d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga49d5a850eb4a63f35e68de89c446878d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MB_CONFIG_MASK</b>&#160;&#160;&#160;0x00000007U /** &lt;Multiband Config mask */</td></tr>
<tr class="separator:ga49d5a850eb4a63f35e68de89c446878d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Invsinc control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure Invsinc. </p>
</div></td></tr>
<tr class="memitem:gaad0e92bc8e42dfaca20bddc7dd1d53b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaad0e92bc8e42dfaca20bddc7dd1d53b8">XRFDC_EN_INVSINC_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaad0e92bc8e42dfaca20bddc7dd1d53b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">invsinc enable mask  <a href="group___overview.html#gaad0e92bc8e42dfaca20bddc7dd1d53b8">More...</a><br/></td></tr>
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<tr class="memitem:ga7956bcab0cdc8a5b307b77d86e7c02ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7956bcab0cdc8a5b307b77d86e7c02ce">XRFDC_MODE_INVSINC_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga7956bcab0cdc8a5b307b77d86e7c02ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">invsinc mode mask  <a href="group___overview.html#ga7956bcab0cdc8a5b307b77d86e7c02ce">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">OBS FIFO start register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure Invsinc. </p>
</div></td></tr>
<tr class="memitem:ga5b871d725c9dd50091c3d69bf72e3ce1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5b871d725c9dd50091c3d69bf72e3ce1">XRFDC_HSCOM_FIFO_START_OBS_EN_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga5b871d725c9dd50091c3d69bf72e3ce1"><td class="mdescLeft">&#160;</td><td class="mdescRight">invsinc enable mask  <a href="group___overview.html#ga5b871d725c9dd50091c3d69bf72e3ce1">More...</a><br/></td></tr>
<tr class="separator:ga5b871d725c9dd50091c3d69bf72e3ce1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1f061563c268ac03b3fd5f37f7c62ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab1f061563c268ac03b3fd5f37f7c62ad">XRFDC_HSCOM_FIFO_START_OBS_EN_SHIFT</a>&#160;&#160;&#160;9U</td></tr>
<tr class="memdesc:gab1f061563c268ac03b3fd5f37f7c62ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">invsinc mode mask  <a href="group___overview.html#gab1f061563c268ac03b3fd5f37f7c62ad">More...</a><br/></td></tr>
<tr class="separator:gab1f061563c268ac03b3fd5f37f7c62ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Signal Detector control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure Signal Detector. </p>
</div></td></tr>
<tr class="memitem:gad6b99afc9c48993a47e79943ebe15a3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad6b99afc9c48993a47e79943ebe15a3c">XRFDC_ADC_SIG_DETECT_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:gad6b99afc9c48993a47e79943ebe15a3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">signal detector mask  <a href="group___overview.html#gad6b99afc9c48993a47e79943ebe15a3c">More...</a><br/></td></tr>
<tr class="separator:gad6b99afc9c48993a47e79943ebe15a3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05aba6291241ac95d2f2761521cf0f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga05aba6291241ac95d2f2761521cf0f19">XRFDC_ADC_SIG_DETECT_THRESH_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:ga05aba6291241ac95d2f2761521cf0f19"><td class="mdescLeft">&#160;</td><td class="mdescRight">signal detector thresholds mask  <a href="group___overview.html#ga05aba6291241ac95d2f2761521cf0f19">More...</a><br/></td></tr>
<tr class="separator:ga05aba6291241ac95d2f2761521cf0f19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga440ea4b17829af23e071df7d20393da9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga440ea4b17829af23e071df7d20393da9">XRFDC_ADC_SIG_DETECT_THRESH_CNT_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:ga440ea4b17829af23e071df7d20393da9"><td class="mdescLeft">&#160;</td><td class="mdescRight">signal detector thresholds counter mask  <a href="group___overview.html#ga440ea4b17829af23e071df7d20393da9">More...</a><br/></td></tr>
<tr class="separator:ga440ea4b17829af23e071df7d20393da9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b757ea8fc8c9f45e60e807efc580948"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5b757ea8fc8c9f45e60e807efc580948">XRFDC_ADC_SIG_DETECT_INTG_MASK</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ga5b757ea8fc8c9f45e60e807efc580948"><td class="mdescLeft">&#160;</td><td class="mdescRight">leaky integrator enable mask  <a href="group___overview.html#ga5b757ea8fc8c9f45e60e807efc580948">More...</a><br/></td></tr>
<tr class="separator:ga5b757ea8fc8c9f45e60e807efc580948"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03c291e964cfdcb58be8f357f9b87c2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03c291e964cfdcb58be8f357f9b87c2b">XRFDC_ADC_SIG_DETECT_FLUSH_MASK</a>&#160;&#160;&#160;0x02</td></tr>
<tr class="memdesc:ga03c291e964cfdcb58be8f357f9b87c2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">leaky integrator flush mask  <a href="group___overview.html#ga03c291e964cfdcb58be8f357f9b87c2b">More...</a><br/></td></tr>
<tr class="separator:ga03c291e964cfdcb58be8f357f9b87c2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga004e0f02e2fefb0988adb1bcdfe14bc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga004e0f02e2fefb0988adb1bcdfe14bc5">XRFDC_ADC_SIG_DETECT_TCONST_MASK</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga004e0f02e2fefb0988adb1bcdfe14bc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">time constant mask  <a href="group___overview.html#ga004e0f02e2fefb0988adb1bcdfe14bc5">More...</a><br/></td></tr>
<tr class="separator:ga004e0f02e2fefb0988adb1bcdfe14bc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0643b9f2df6749b93ae6c05974556f6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0643b9f2df6749b93ae6c05974556f6a">XRFDC_ADC_SIG_DETECT_MODE_MASK</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga0643b9f2df6749b93ae6c05974556f6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">mode mask  <a href="group___overview.html#ga0643b9f2df6749b93ae6c05974556f6a">More...</a><br/></td></tr>
<tr class="separator:ga0643b9f2df6749b93ae6c05974556f6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1968900e0e5d6e0a8e8e8f7b6cfc1ba2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1968900e0e5d6e0a8e8e8f7b6cfc1ba2">XRFDC_ADC_SIG_DETECT_HYST_MASK</a>&#160;&#160;&#160;0x80</td></tr>
<tr class="memdesc:ga1968900e0e5d6e0a8e8e8f7b6cfc1ba2"><td class="mdescLeft">&#160;</td><td class="mdescRight">hysteresis enable mask  <a href="group___overview.html#ga1968900e0e5d6e0a8e8e8f7b6cfc1ba2">More...</a><br/></td></tr>
<tr class="separator:ga1968900e0e5d6e0a8e8e8f7b6cfc1ba2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72de774c29f6670c78dc515fafd0c9fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga72de774c29f6670c78dc515fafd0c9fb">XRFDC_ADC_SIG_DETECT_INTG_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga72de774c29f6670c78dc515fafd0c9fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">leaky integrator enable shift  <a href="group___overview.html#ga72de774c29f6670c78dc515fafd0c9fb">More...</a><br/></td></tr>
<tr class="separator:ga72de774c29f6670c78dc515fafd0c9fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3499da9ecc7697df2fd74dc6a9ba5cf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3499da9ecc7697df2fd74dc6a9ba5cf2">XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga3499da9ecc7697df2fd74dc6a9ba5cf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">leaky integrator flush shift  <a href="group___overview.html#ga3499da9ecc7697df2fd74dc6a9ba5cf2">More...</a><br/></td></tr>
<tr class="separator:ga3499da9ecc7697df2fd74dc6a9ba5cf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga75f6b7dcdb1a3cc785432c46b014be86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga75f6b7dcdb1a3cc785432c46b014be86">XRFDC_ADC_SIG_DETECT_TCONST_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga75f6b7dcdb1a3cc785432c46b014be86"><td class="mdescLeft">&#160;</td><td class="mdescRight">time constant shift  <a href="group___overview.html#ga75f6b7dcdb1a3cc785432c46b014be86">More...</a><br/></td></tr>
<tr class="separator:ga75f6b7dcdb1a3cc785432c46b014be86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5cd37568b27e481f154240b6af805ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac5cd37568b27e481f154240b6af805ee">XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gac5cd37568b27e481f154240b6af805ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">mode shift fror writing  <a href="group___overview.html#gac5cd37568b27e481f154240b6af805ee">More...</a><br/></td></tr>
<tr class="separator:gac5cd37568b27e481f154240b6af805ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga080ab8dffb3fe4c83877460340ccc152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga080ab8dffb3fe4c83877460340ccc152">XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga080ab8dffb3fe4c83877460340ccc152"><td class="mdescLeft">&#160;</td><td class="mdescRight">mode shift fror reading  <a href="group___overview.html#ga080ab8dffb3fe4c83877460340ccc152">More...</a><br/></td></tr>
<tr class="separator:ga080ab8dffb3fe4c83877460340ccc152"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga978446cb2a2a046e1874c33b4313701f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga978446cb2a2a046e1874c33b4313701f">XRFDC_ADC_SIG_DETECT_HYST_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga978446cb2a2a046e1874c33b4313701f"><td class="mdescLeft">&#160;</td><td class="mdescRight">hysteresis enable shift  <a href="group___overview.html#ga978446cb2a2a046e1874c33b4313701f">More...</a><br/></td></tr>
<tr class="separator:ga978446cb2a2a046e1874c33b4313701f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">CLK_DIV register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the bits to control the clock divider providing the clock fabric out. </p>
</div></td></tr>
<tr class="memitem:ga52c4f21e7634a425f4bcef5885b1df37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga52c4f21e7634a425f4bcef5885b1df37">XRFDC_FAB_CLK_DIV_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga52c4f21e7634a425f4bcef5885b1df37"><td class="mdescLeft">&#160;</td><td class="mdescRight">clk div mask  <a href="group___overview.html#ga52c4f21e7634a425f4bcef5885b1df37">More...</a><br/></td></tr>
<tr class="separator:ga52c4f21e7634a425f4bcef5885b1df37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10c03b9b48706e597d14f262eff7c2bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga10c03b9b48706e597d14f262eff7c2bc">XRFDC_FAB_CLK_DIV_CAL_MASK</a>&#160;&#160;&#160;0x000000F0U</td></tr>
<tr class="memdesc:ga10c03b9b48706e597d14f262eff7c2bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">clk div cal mask  <a href="group___overview.html#ga10c03b9b48706e597d14f262eff7c2bc">More...</a><br/></td></tr>
<tr class="separator:ga10c03b9b48706e597d14f262eff7c2bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95588d2e87659856c4c00ce3aa52f911"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga95588d2e87659856c4c00ce3aa52f911">XRFDC_FAB_CLK_DIV_SYNC_PULSE_MASK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga95588d2e87659856c4c00ce3aa52f911"><td class="mdescLeft">&#160;</td><td class="mdescRight">clk div cal mask  <a href="group___overview.html#ga95588d2e87659856c4c00ce3aa52f911">More...</a><br/></td></tr>
<tr class="separator:ga95588d2e87659856c4c00ce3aa52f911"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Multiband Config</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure multiband for DAC. </p>
</div></td></tr>
<tr class="memitem:ga59d59668d91184589c77722057aa98f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga59d59668d91184589c77722057aa98f7">XRFDC_MB_CFG_MASK</a>&#160;&#160;&#160;0x000001FFU</td></tr>
<tr class="memdesc:ga59d59668d91184589c77722057aa98f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">MB config mask.  <a href="group___overview.html#ga59d59668d91184589c77722057aa98f7">More...</a><br/></td></tr>
<tr class="separator:ga59d59668d91184589c77722057aa98f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ec7ae3594537b9fbbb13258b55c8bf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9ec7ae3594537b9fbbb13258b55c8bf6">XRFDC_MB_EN_4X_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga9ec7ae3594537b9fbbb13258b55c8bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable 4X MB mask.  <a href="group___overview.html#ga9ec7ae3594537b9fbbb13258b55c8bf6">More...</a><br/></td></tr>
<tr class="separator:ga9ec7ae3594537b9fbbb13258b55c8bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Multi Tile Sync</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Multi-Tile Sync bit masks. </p>
</div></td></tr>
<tr class="memitem:gab1e8a635346fdbc0eb53647ae4c7b407"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1e8a635346fdbc0eb53647ae4c7b407"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_PLL_M</b>&#160;&#160;&#160;0x0100U</td></tr>
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<tr class="memitem:ga93028e523c1f54c10288bdc074399965"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga93028e523c1f54c10288bdc074399965"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_DIG_M</b>&#160;&#160;&#160;0x0100U</td></tr>
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<tr class="memitem:ga21fc8b38692f63400591d8c365ab0be4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga21fc8b38692f63400591d8c365ab0be4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_EN_TRX_M</b>&#160;&#160;&#160;0x0400U</td></tr>
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<tr class="memitem:ga1cb0ee0d4aad8119068c2830a2c0810c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1cb0ee0d4aad8119068c2830a2c0810c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCAP_INIT_M</b>&#160;&#160;&#160;0x8200U</td></tr>
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<tr class="memitem:gad08d1c41d781474e31e83b15270c667c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad08d1c41d781474e31e83b15270c667c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCLR_T1_M</b>&#160;&#160;&#160;0x2000U</td></tr>
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<tr class="memitem:ga223a0276cb6add726d802b5d36cae413"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga223a0276cb6add726d802b5d36cae413"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCLR_PLL_M</b>&#160;&#160;&#160;0x0200U</td></tr>
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<tr class="memitem:gaffd4416e8fb6329bc4afe2d6a8e193c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaffd4416e8fb6329bc4afe2d6a8e193c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_PLLEN_M</b>&#160;&#160;&#160;0x0001U</td></tr>
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<tr class="memitem:ga81ec3e652fc114de4bfa6931dbf0ad06"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81ec3e652fc114de4bfa6931dbf0ad06"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_SRCOUNT_M</b>&#160;&#160;&#160;0x00FFU</td></tr>
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<tr class="memitem:ga0b4856022cfac51833ec5f32197cb483"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0b4856022cfac51833ec5f32197cb483"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_DELAY_VAL_M</b>&#160;&#160;&#160;0x041FU</td></tr>
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<tr class="memitem:ga54d75545f11920e44a990d733649d779"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga54d75545f11920e44a990d733649d779"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_AMARK_CNT_M</b>&#160;&#160;&#160;0x00FFU</td></tr>
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<tr class="memitem:ga07b4b123b159a5d35edbb454274f781a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07b4b123b159a5d35edbb454274f781a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_AMARK_LOC_M</b>&#160;&#160;&#160;0x0F0000U</td></tr>
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<tr class="memitem:ga59e76de469edc59053bdc359bbb95706"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga59e76de469edc59053bdc359bbb95706"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_MTS_AMARK_DONE_M</b>&#160;&#160;&#160;0x100000U</td></tr>
<tr class="separator:ga59e76de469edc59053bdc359bbb95706"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Output divider LSB register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to configure output divisor </p>
</div></td></tr>
<tr class="memitem:ga3065acbdfe8190f0ac269a57835c607b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3065acbdfe8190f0ac269a57835c607b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_MASK</b>&#160;&#160;&#160;0x0CFFU</td></tr>
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<tr class="memitem:ga07f6ac45a0508ef7ce0f8bc60a73891b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07f6ac45a0508ef7ce0f8bc60a73891b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_MODE_MASK</b>&#160;&#160;&#160;0x00C0U</td></tr>
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<tr class="memitem:gace5b28eb33d2c4ed162d0b3094d87d7e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gace5b28eb33d2c4ed162d0b3094d87d7e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_BYP_OPDIV_MASK</b>&#160;&#160;&#160;0x0400U</td></tr>
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<tr class="memitem:gaebe9ae83a22530390d636cf3b0483a71"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaebe9ae83a22530390d636cf3b0483a71"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_BYP_PLL_MASK</b>&#160;&#160;&#160;0x0800U</td></tr>
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<tr class="memitem:gadfc64d74c1eac69f7bef22cf21728a0a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadfc64d74c1eac69f7bef22cf21728a0a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_VALUE_MASK</b>&#160;&#160;&#160;0x003FU</td></tr>
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<tr class="memitem:ga290d5340e69b254a37ac0fe32de3214a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga290d5340e69b254a37ac0fe32de3214a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XRFDC_PLL_DIVIDER0_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
<tr class="separator:ga290d5340e69b254a37ac0fe32de3214a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Multi-tile sync and clock source control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits to Multi-tile sync and clock source control </p>
</div></td></tr>
<tr class="memitem:ga3790dd8f680e9af869bda4c1d1c80fbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3790dd8f680e9af869bda4c1d1c80fbe">XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK</a>&#160;&#160;&#160;0x1U</td></tr>
<tr class="memdesc:ga3790dd8f680e9af869bda4c1d1c80fbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL clock mask.  <a href="group___overview.html#ga3790dd8f680e9af869bda4c1d1c80fbe">More...</a><br/></td></tr>
<tr class="separator:ga3790dd8f680e9af869bda4c1d1c80fbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3108ad477c74ec5dc3141a8289f9caec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3108ad477c74ec5dc3141a8289f9caec">XRFDC_CLK_NETWORK_CTRL1_USE_RX_MASK</a>&#160;&#160;&#160;0x2U</td></tr>
<tr class="memdesc:ga3108ad477c74ec5dc3141a8289f9caec"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL clock mask.  <a href="group___overview.html#ga3108ad477c74ec5dc3141a8289f9caec">More...</a><br/></td></tr>
<tr class="separator:ga3108ad477c74ec5dc3141a8289f9caec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1a4a19cac86215c9885cac5782013282"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1a4a19cac86215c9885cac5782013282">XRFDC_CLK_NETWORK_CTRL1_REGS_MASK</a>&#160;&#160;&#160;0x3U</td></tr>
<tr class="memdesc:ga1a4a19cac86215c9885cac5782013282"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL clock mask.  <a href="group___overview.html#ga1a4a19cac86215c9885cac5782013282">More...</a><br/></td></tr>
<tr class="separator:ga1a4a19cac86215c9885cac5782013282"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87de04d84796537135aaea9a18a8632f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga87de04d84796537135aaea9a18a8632f">XRFDC_CLK_NETWORK_CTRL1_EN_SYNC_MASK</a>&#160;&#160;&#160;0x1000U</td></tr>
<tr class="memdesc:ga87de04d84796537135aaea9a18a8632f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL clock mask.  <a href="group___overview.html#ga87de04d84796537135aaea9a18a8632f">More...</a><br/></td></tr>
<tr class="separator:ga87de04d84796537135aaea9a18a8632f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">PLL_CRS1 - PLL CRS1 register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for VCO sel_auto, VCO band selection etc., </p>
</div></td></tr>
<tr class="memitem:ga29c9685a174240f1a8af67635b0c87d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga29c9685a174240f1a8af67635b0c87d6">XRFDC_PLL_CRS1_VCO_SEL_MASK</a>&#160;&#160;&#160;0x00008001U</td></tr>
<tr class="memdesc:ga29c9685a174240f1a8af67635b0c87d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">VCO SEL Mask.  <a href="group___overview.html#ga29c9685a174240f1a8af67635b0c87d6">More...</a><br/></td></tr>
<tr class="separator:ga29c9685a174240f1a8af67635b0c87d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f26a8cbe0a9484cade2494677315280"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2f26a8cbe0a9484cade2494677315280">XRFDC_PLL_VCO_SEL_AUTO_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga2f26a8cbe0a9484cade2494677315280"><td class="mdescLeft">&#160;</td><td class="mdescRight">VCO Auto SEL Mask.  <a href="group___overview.html#ga2f26a8cbe0a9484cade2494677315280">More...</a><br/></td></tr>
<tr class="separator:ga2f26a8cbe0a9484cade2494677315280"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader"></div></td></tr>
<tr class="memitem:gab2512f0e32121881f18a53041d10b07b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab2512f0e32121881f18a53041d10b07b">XRFDC_DIGI_ANALOG_SHIFT4</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:gab2512f0e32121881f18a53041d10b07b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register bits Shift, Width Masks.  <a href="group___overview.html#gab2512f0e32121881f18a53041d10b07b">More...</a><br/></td></tr>
<tr class="separator:gab2512f0e32121881f18a53041d10b07b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Delays</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for delaying the FIFOs., </p>
</div></td></tr>
<tr class="memitem:gaae0a17b4e267d142c16acf921558ea49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaae0a17b4e267d142c16acf921558ea49">XRFDC_DAC_FIFO_DELAY_MASK</a>&#160;&#160;&#160;0x000000FFFU</td></tr>
<tr class="memdesc:gaae0a17b4e267d142c16acf921558ea49"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC FIFO ReadPtr Delay.  <a href="group___overview.html#gaae0a17b4e267d142c16acf921558ea49">More...</a><br/></td></tr>
<tr class="separator:gaae0a17b4e267d142c16acf921558ea49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad17c6046a8e2e30eac240d44d3aa2fae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad17c6046a8e2e30eac240d44d3aa2fae">XRFDC_ADC_FIFO_DELAY_MASK</a>&#160;&#160;&#160;0x0000001C0U</td></tr>
<tr class="memdesc:gad17c6046a8e2e30eac240d44d3aa2fae"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO ReadPtr Delay.  <a href="group___overview.html#gad17c6046a8e2e30eac240d44d3aa2fae">More...</a><br/></td></tr>
<tr class="separator:gad17c6046a8e2e30eac240d44d3aa2fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc849ea943b6f593e3cd20a86c427a79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabc849ea943b6f593e3cd20a86c427a79">XRFDC_ADC_FIFO_DELAY_SHIFT</a>&#160;&#160;&#160;6U</td></tr>
<tr class="memdesc:gabc849ea943b6f593e3cd20a86c427a79"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC FIFO ReadPtr Shift.  <a href="group___overview.html#gabc849ea943b6f593e3cd20a86c427a79">More...</a><br/></td></tr>
<tr class="separator:gabc849ea943b6f593e3cd20a86c427a79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Scaler register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the data scaler ebable bit. </p>
</div></td></tr>
<tr class="memitem:gad810f517dc30f2c632ad8ba4066780e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad810f517dc30f2c632ad8ba4066780e5">XRFDC_DATA_SCALER_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gad810f517dc30f2c632ad8ba4066780e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock detect mask.  <a href="group___overview.html#gad810f517dc30f2c632ad8ba4066780e5">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Calibration divider bypass register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the calibration divider bypass enable bit. </p>
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<tr class="memitem:ga6a63306f7e07c4f088eccfe0c83f5caf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6a63306f7e07c4f088eccfe0c83f5caf">XRFDC_CAL_DIV_BYP_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
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